| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 126 .dppclk_mhz = 1200.0,
135 .dppclk_mhz = 1200.0,
144 .dppclk_mhz = 1200.0,
153 .dppclk_mhz = 1200.0,
162 .dppclk_mhz = 1200.0,
370 .dppclk_mhz = 556.0,
379 .dppclk_mhz = 625.0,
388 .dppclk_mhz = 625.0,
397 .dppclk_mhz = 1112.0,
406 .dppclk_mhz = 1250.0,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 121 .dppclk_mhz = 1015.0,
133 .dppclk_mhz = 1015.0,
145 .dppclk_mhz = 1015.0,
157 .dppclk_mhz = 1015.0,
169 .dppclk_mhz = 1015.0,
346 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn301_fpu_update_bw_bounding_box()
347 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn301_fpu_update_bw_bounding_box()
369 s[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : in dcn301_fpu_update_bw_bounding_box()
370 dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn301_fpu_update_bw_bounding_box()
472 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_fpu_calculate_wm_and_dlg()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 106 .dppclk_mhz = 600.0,
119 .dppclk_mhz = 800.0,
132 .dppclk_mhz = 800.0,
145 .dppclk_mhz = 960.0,
158 .dppclk_mhz = 1066.7,
171 .dppclk_mhz = 1200.0,
184 .dppclk_mhz = 1371.4,
197 .dppclk_mhz = 1600.0,
284 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn351_update_bw_bounding_box_fpu()
285 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn351_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 107 .dppclk_mhz = 1200.0,
116 .dppclk_mhz = 1200.0,
125 .dppclk_mhz = 1200.0,
134 .dppclk_mhz = 1200.0,
143 .dppclk_mhz = 1200.0,
211 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn314_update_bw_bounding_box_fpu()
212 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn314_update_bw_bounding_box_fpu()
247 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : in dcn314_update_bw_bounding_box_fpu()
248 dcn3_14_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn314_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 123 .dppclk_mhz = 1200.0,
132 .dppclk_mhz = 1200.0,
141 .dppclk_mhz = 1200.0,
150 .dppclk_mhz = 1200.0,
159 .dppclk_mhz = 1200.0,
250 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn35_update_bw_bounding_box_fpu()
251 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn35_update_bw_bounding_box_fpu()
297 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? in dcn35_update_bw_bounding_box_fpu()
299 dcn3_5_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn35_update_bw_bounding_box_fpu()
364 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz = in dcn35_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 228 .dppclk_mhz = 513.0,
239 .dppclk_mhz = 642.0,
250 .dppclk_mhz = 734.0,
261 .dppclk_mhz = 1100.0,
272 .dppclk_mhz = 1284.0,
284 .dppclk_mhz = 1284.0,
339 .dppclk_mhz = 513.0,
350 .dppclk_mhz = 642.0,
361 .dppclk_mhz = 734.0,
372 .dppclk_mhz = 1100.0,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/ |
| H A D | dcn401_soc_and_ip_translator.c | 140 if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dppclk_mhz && in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
141 dc_clk_table->entries[i].dppclk_mhz > dc_bw_params->dc_mode_limit.dppclk_mhz) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
142 if (i == 0 || dc_clk_table->entries[i-1].dppclk_mhz < dc_bw_params->dc_mode_limit.dppclk_mhz) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
143 dml_clk_table->dppclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dppclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
150 dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 112 .dppclk_mhz = 1720.0,
373 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz) in build_synthetic_soc_states()
374 max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in build_synthetic_soc_states()
413 if (max_clk_data.dppclk_mhz == 0) in build_synthetic_soc_states()
414 max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz; in build_synthetic_soc_states()
427 entry.dppclk_mhz = max_clk_data.dppclk_mhz; in build_synthetic_soc_states()
726 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn321_update_bw_bounding_box_fpu()
727 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn321_update_bw_bounding_box_fpu()
736 max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; in dcn321_update_bw_bounding_box_fpu()
824 dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn321_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 118 .dppclk_mhz = 300.0,
228 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_fpu_update_bw_bounding_box()
229 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
238 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
326 dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 117 .dppclk_mhz = 300.0,
224 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn303_fpu_update_bw_bounding_box()
225 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
234 max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
332 dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 130 .dppclk_mhz = 300.0,
483 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn30_fpu_calculate_wm_and_dlg()
487 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
491 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn30_fpu_calculate_wm_and_dlg()
492 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn30_fpu_calculate_wm_and_dlg()
539 dcn30_bb_max_clk->max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_update_max_clk()
589 dcn3_0_soc.clock_limits[i].dppclk_mhz = dcn30_bb_max_clk->max_dppclk_mhz; in dcn30_fpu_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 223 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn32_init_clocks()
226 …clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()
228 if (clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz > 1950) in dcn32_init_clocks()
229 clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = 1950; in dcn32_init_clocks()
249 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz in dcn32_init_clocks()
251 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz in dcn32_init_clocks()
256 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz > 1950) in dcn32_init_clocks()
257 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz = 1950; in dcn32_init_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 133 .dppclk_mhz = 2150.0,
1524 pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0); in dcn32_full_validate_bw_helper()
1724 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn32_calculate_dlg_params()
1725 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn32_calculate_dlg_params()
1727 … context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn32_calculate_dlg_params()
1780 …w_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz in dcn32_calculate_dlg_params()
2600 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn32_calculate_wm_and_dlg_fpu()
2604 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
2608 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn32_calculate_wm_and_dlg_fpu()
2609 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn32_calculate_wm_and_dlg_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_policy.c | 147 if (p->in_states->state_array[i].dppclk_mhz > max_dppclk_mhz) in dml2_policy_build_synthetic_soc_states()
148 max_dppclk_mhz = (int) p->in_states->state_array[i].dppclk_mhz; in dml2_policy_build_synthetic_soc_states()
168 s->entry.dppclk_mhz = max_dppclk_mhz; in dml2_policy_build_synthetic_soc_states()
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| H A D | dml2_translation_helper.c | 369 p->in_states->state_array[0].dppclk_mhz = 2150.0; in dml2_init_soc_states()
405 p->in_states->state_array[0].dppclk_mhz = 1720.0; in dml2_init_soc_states()
442 p->in_states->state_array[0].dppclk_mhz = 2000; //2150.0; in dml2_init_soc_states()
557 p->in_states->state_array[i].dppclk_mhz = in dml2_init_soc_states()
558 dml2->config.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz; in dml2_init_soc_states()
579 if (p->in_states->state_array[i].dppclk_mhz > max_dppclk_mhz) in dml2_init_soc_states()
580 max_dppclk_mhz = (int)p->in_states->state_array[i].dppclk_mhz; in dml2_init_soc_states()
592 p->out_states->state_array[i].dppclk_mhz = max_dppclk_mhz; in dml2_init_soc_states()
724 out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz; in dml2_translate_soc_states()
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| H A D | display_mode_util.c | 630 dml_print("DML: state_bbox: dppclk_mhz = %f\n", state->dppclk_mhz); in dml_print_soc_state_bounding_box()
698 dml_print("DML: clk_cfg: i=%d, dppclk_mhz = %f\n", i, clk_cfg->dppclk_mhz[i]); in dml_print_clk_cfg()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 35 uint32_t dppclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 168 double dppclk_mhz; member
550 double dppclk_mhz; member
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| H A D | display_mode_vba.c | 68 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()
401 mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz; in fetch_socbb_params()
707 mode_lib->vba.DPPCLK[mode_lib->vba.NumberOfActivePlanes] = clks->dppclk_mhz; in fetch_pipe_params()
1109 if (mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz > 0.0) in ModeSupportAndSystemConfiguration()
1110 mode_lib->vba.DPPCLK[k] = mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz; in ModeSupportAndSystemConfiguration()
1112 mode_lib->vba.DPPCLK[k] = soc->clock_limits[mode_lib->vba.VoltageLevel].dppclk_mhz; in ModeSupportAndSystemConfiguration()
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| H A D | display_mode_lib.c | 278 dml_print("DML PARAMS: dppclk_mhz = %3.2f\n", clks_cfg->dppclk_mhz); in dml_log_pipe_params()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 147 .dppclk_mhz = 300.0,
158 .dppclk_mhz = 1200.0,
169 .dppclk_mhz = 1200.0,
180 .dppclk_mhz = 1200.0,
192 .dppclk_mhz = 1200.0,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 1097 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; in dcn35_clk_mgr_helper_populate_bw_params()
1118 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; in dcn35_clk_mgr_helper_populate_bw_params()
1130 bw_params->clk_table.entries[i].dppclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()
1161 if (!bw_params->clk_table.entries[i].dppclk_mhz) in dcn35_clk_mgr_helper_populate_bw_params()
1162 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1311 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 : in dcn35_get_max_clock_khz()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 123 unsigned int dppclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 607 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; in vg_clk_mgr_helper_populate_bw_params()
614 …bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, VG_NUM_DPP… in vg_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 283 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn401_init_clocks()
301 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz in dcn401_init_clocks()
303 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz in dcn401_init_clocks()
1514 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 : in dcn401_get_max_clock_khz()
|