xref: /linux/drivers/accel/amdxdna/npu1_regs.c (revision dfb31428444b00824b161d8c0741d4868552813a)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
4  */
5 
6 #include <drm/amdxdna_accel.h>
7 #include <drm/drm_device.h>
8 #include <drm/gpu_scheduler.h>
9 #include <linux/bits.h>
10 #include <linux/sizes.h>
11 
12 #include "aie2_pci.h"
13 #include "amdxdna_mailbox.h"
14 #include "amdxdna_pci_drv.h"
15 
16 /* Address definition from NPU1 docs */
17 #define MPNPU_PWAITMODE			0x3010034
18 #define MPNPU_PUB_SEC_INTR		0x3010090
19 #define MPNPU_PUB_PWRMGMT_INTR		0x3010094
20 #define MPNPU_PUB_SCRATCH2		0x30100A0
21 #define MPNPU_PUB_SCRATCH3		0x30100A4
22 #define MPNPU_PUB_SCRATCH4		0x30100A8
23 #define MPNPU_PUB_SCRATCH5		0x30100AC
24 #define MPNPU_PUB_SCRATCH6		0x30100B0
25 #define MPNPU_PUB_SCRATCH7		0x30100B4
26 #define MPNPU_PUB_SCRATCH9		0x30100BC
27 
28 #define MPNPU_SRAM_X2I_MAILBOX_0	0x30A0000
29 #define MPNPU_SRAM_X2I_MAILBOX_1	0x30A2000
30 #define MPNPU_SRAM_I2X_MAILBOX_15	0x30BF000
31 
32 #define MPNPU_APERTURE0_BASE		0x3000000
33 #define MPNPU_APERTURE1_BASE		0x3080000
34 #define MPNPU_APERTURE2_BASE		0x30C0000
35 
36 /* PCIe BAR Index for NPU1 */
37 #define NPU1_REG_BAR_INDEX  0
38 #define NPU1_MBOX_BAR_INDEX 4
39 #define NPU1_PSP_BAR_INDEX  0
40 #define NPU1_SMU_BAR_INDEX  0
41 #define NPU1_SRAM_BAR_INDEX 2
42 /* Associated BARs and Apertures */
43 #define NPU1_REG_BAR_BASE  MPNPU_APERTURE0_BASE
44 #define NPU1_MBOX_BAR_BASE MPNPU_APERTURE2_BASE
45 #define NPU1_PSP_BAR_BASE  MPNPU_APERTURE0_BASE
46 #define NPU1_SMU_BAR_BASE  MPNPU_APERTURE0_BASE
47 #define NPU1_SRAM_BAR_BASE MPNPU_APERTURE1_BASE
48 
49 const struct rt_config npu1_default_rt_cfg[] = {
50 	{ 2, 1, AIE2_RT_CFG_INIT }, /* PDI APP LOAD MODE */
51 	{ 4, 1, AIE2_RT_CFG_INIT }, /* Debug BO */
52 	{ 1, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
53 	{ 0 },
54 };
55 
56 const struct dpm_clk_freq npu1_dpm_clk_table[] = {
57 	{400, 800},
58 	{600, 1024},
59 	{600, 1024},
60 	{600, 1024},
61 	{600, 1024},
62 	{720, 1309},
63 	{720, 1309},
64 	{847, 1600},
65 	{ 0 }
66 };
67 
68 static const struct aie2_fw_feature_tbl npu1_fw_feature_table[] = {
69 	{ .major = 5, .min_minor = 7 },
70 	{ .features = BIT_U64(AIE2_NPU_COMMAND), .major = 5, .min_minor = 8 },
71 	{ 0 }
72 };
73 
74 static const struct amdxdna_dev_priv npu1_dev_priv = {
75 	.fw_path        = "amdnpu/1502_00/",
76 	.rt_config	= npu1_default_rt_cfg,
77 	.dpm_clk_tbl	= npu1_dpm_clk_table,
78 	.fw_feature_tbl = npu1_fw_feature_table,
79 	.col_align	= COL_ALIGN_NONE,
80 	.mbox_dev_addr  = NPU1_MBOX_BAR_BASE,
81 	.mbox_size      = 0, /* Use BAR size */
82 	.sram_dev_addr  = NPU1_SRAM_BAR_BASE,
83 	.hwctx_limit    = 6,
84 	.sram_offs      = {
85 		DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU1_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
86 		DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU1_SRAM, MPNPU_SRAM_I2X_MAILBOX_15),
87 	},
88 	.psp_regs_off   = {
89 		DEFINE_BAR_OFFSET(PSP_CMD_REG,    NPU1_PSP, MPNPU_PUB_SCRATCH2),
90 		DEFINE_BAR_OFFSET(PSP_ARG0_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH3),
91 		DEFINE_BAR_OFFSET(PSP_ARG1_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH4),
92 		DEFINE_BAR_OFFSET(PSP_ARG2_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH9),
93 		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU1_PSP, MPNPU_PUB_SEC_INTR),
94 		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU1_PSP, MPNPU_PUB_SCRATCH2),
95 		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH3),
96 		DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU1_PSP, MPNPU_PWAITMODE),
97 	},
98 	.smu_regs_off   = {
99 		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH5),
100 		DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH7),
101 		DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU1_SMU, MPNPU_PUB_PWRMGMT_INTR),
102 		DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU1_SMU, MPNPU_PUB_SCRATCH6),
103 		DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH7),
104 	},
105 	.hw_ops		= {
106 		.set_dpm = npu1_set_dpm,
107 	},
108 };
109 
110 const struct amdxdna_dev_info dev_npu1_info = {
111 	.reg_bar           = NPU1_REG_BAR_INDEX,
112 	.mbox_bar          = NPU1_MBOX_BAR_INDEX,
113 	.sram_bar          = NPU1_SRAM_BAR_INDEX,
114 	.psp_bar           = NPU1_PSP_BAR_INDEX,
115 	.smu_bar           = NPU1_SMU_BAR_INDEX,
116 	.first_col         = 1,
117 	.dev_mem_buf_shift = 15, /* 32 KiB aligned */
118 	.dev_mem_base      = AIE2_DEVM_BASE,
119 	.dev_mem_size      = AIE2_DEVM_SIZE,
120 	.vbnv              = "RyzenAI-npu1",
121 	.device_type       = AMDXDNA_DEV_TYPE_KMQ,
122 	.dev_priv          = &npu1_dev_priv,
123 	.ops               = &aie2_ops,
124 };
125