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Searched refs:dpcd (Results 1 – 25 of 45) sorted by relevance

12

/linux/include/drm/display/
H A Ddrm_dp_helper.h48 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
50 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
54 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
57 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
135 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
136 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
141 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate()
143 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate()
147 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count()
149 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_dp.c42 return drm_dp_read_sink_count_cap(connector, outp->dp.dpcd, &outp->dp.desc); in nouveau_dp_has_sink_count()
69 u8 *dpcd = outp->dp.dpcd; in nouveau_dp_probe_dpcd() local
78 !drm_dp_read_dpcd_caps(aux, dpcd) && in nouveau_dp_probe_dpcd()
79 !drm_dp_read_lttpr_common_caps(aux, dpcd, outp->dp.lttpr.caps)) { in nouveau_dp_probe_dpcd()
86 ret = drm_dp_read_dpcd_caps(aux, dpcd); in nouveau_dp_probe_dpcd()
90 outp->dp.link_nr = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in nouveau_dp_probe_dpcd()
101 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP && dpcd[DP_DPCD_REV] >= 0x13) { in nouveau_dp_probe_dpcd()
121 outp->dp.rate[j].dpcd = i; in nouveau_dp_probe_dpcd()
130 u32 max_rate = dpcd[DP_MAX_LINK_RATE] * 27000; in nouveau_dp_probe_dpcd()
143 outp->dp.rate[outp->dp.rate_nr].dpcd = -1; in nouveau_dp_probe_dpcd()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c253 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_link_config()
260 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
261 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
322 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in amdgpu_atombios_dp_probe_oui()
339 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) { in amdgpu_atombios_dp_ds_ports()
359 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd()
361 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in amdgpu_atombios_dp_get_dpcd()
362 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd()
369 dig_connector->dpcd[0] = 0; in amdgpu_atombios_dp_get_dpcd()
421 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, in amdgpu_atombios_dp_set_link_config()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Datombios_dp.c302 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config()
308 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config()
309 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config()
370 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in radeon_dp_probe_oui()
391 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
393 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in radeon_dp_getdpcd()
394 dig_connector->dpcd); in radeon_dp_getdpcd()
401 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
458 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_set_link_config()
485 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_mode_valid_helper()
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix-anx6345.c63 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
99 u8 dp_bw, dpcd[2]; in anx6345_dp_link_training() local
134 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); in anx6345_dp_link_training()
146 drm_dp_link_power_up(&anx6345->aux, anx6345->dpcd[DP_DPCD_REV]); in anx6345_dp_link_training()
154 if (anx6345->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { in anx6345_dp_link_training()
173 if (drm_dp_enhanced_frame_cap(anx6345->dpcd)) in anx6345_dp_link_training()
184 dpcd[0] = dp_bw; in anx6345_dp_link_training()
186 SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]); in anx6345_dp_link_training()
190 dpcd[1] = drm_dp_max_lane_count(anx6345->dpcd); in anx6345_dp_link_training()
193 SP_DP_LANE_COUNT_SET_REG, dpcd[1]); in anx6345_dp_link_training()
[all …]
H A Danalogix-anx78xx.c83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
606 u8 dp_bw, dpcd[2]; in anx78xx_dp_link_training() local
647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); in anx78xx_dp_link_training()
659 drm_dp_link_power_up(&anx78xx->aux, anx78xx->dpcd[DP_DPCD_REV]); in anx78xx_dp_link_training()
667 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { in anx78xx_dp_link_training()
686 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) in anx78xx_dp_link_training()
699 anx78xx->dpcd[DP_MAX_LINK_RATE]); in anx78xx_dp_link_training()
703 dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd); in anx78xx_dp_link_training()
705 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) in anx78xx_dp_link_training()
706 dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; in anx78xx_dp_link_training()
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.c242 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 && in nvkm_dp_train_eq()
243 lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED) in nvkm_dp_train_eq()
246 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 && in nvkm_dp_train_eq()
247 lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
252 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_eq()
284 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater) in nvkm_dp_train_cr()
285 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_cr()
318 .pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED, in nvkm_dp_train_link()
327 sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0; in nvkm_dp_train_link()
338 if (outp->dp.rate[rate].dpcd >= 0) { in nvkm_dp_train_link()
[all …]
H A Doutp.h48 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
51 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ member
H A Duoutp.c90 outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP, in nvkm_uoutp_mthd_dp_sst()
118 memcpy(outp->dp.dpcd, args->v0.dpcd, sizeof(outp->dp.dpcd)); in nvkm_uoutp_mthd_dp_train()
140 outp->dp.rate[i].dpcd = args->v0.rate[i].dpcd; in nvkm_uoutp_mthd_dp_rates()
/linux/drivers/gpu/drm/tegra/
H A Ddp.c172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe() local
178 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd)); in drm_dp_link_probe()
182 link->revision = dpcd[DP_DPCD_REV]; in drm_dp_link_probe()
183 link->max_rate = drm_dp_max_link_rate(dpcd); in drm_dp_link_probe()
184 link->max_lanes = drm_dp_max_lane_count(dpcd); in drm_dp_link_probe()
186 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); in drm_dp_link_probe()
187 link->caps.tps3_supported = drm_dp_tps3_supported(dpcd); in drm_dp_link_probe()
188 link->caps.fast_training = drm_dp_fast_training_cap(dpcd); in drm_dp_link_probe()
189 link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); in drm_dp_link_probe()
191 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { in drm_dp_link_probe()
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c264 uint8_t dpcd[4]; member
327 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in cdv_intel_dp_max_lane_count()
328 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; in cdv_intel_dp_max_lane_count()
343 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; in cdv_intel_dp_max_link_bw()
1075 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && in cdv_intel_dp_mode_set()
1076 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { in cdv_intel_dp_mode_set()
1111 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in cdv_intel_dp_sink_dpms()
1670 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd, in cdv_dp_detect()
1671 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) in cdv_dp_detect()
1673 if (intel_dp->dpcd[DP_DPCD_REV] != 0) in cdv_dp_detect()
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/linux/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_link.c213 drm_dp_link_train_clock_recovery_delay(dp->aux, dp->dpcd); in hibmc_dp_link_training_cr()
266 drm_dp_link_train_channel_eq_delay(dp->aux, dp->dpcd); in hibmc_dp_link_training_channel_eq()
330 dp->link.cap.link_rate = dp->dpcd[DP_MAX_LINK_RATE]; in hibmc_dp_update_caps()
334 dp->link.cap.lanes = dp->dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in hibmc_dp_update_caps()
344 ret = drm_dp_read_dpcd_caps(dp->aux, dp->dpcd); in hibmc_dp_link_training()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp.c180 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in max_dprx_rate()
199 return drm_dp_max_lane_count(intel_dp->dpcd); in max_dprx_lane_count()
245 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { in intel_dp_set_dpcd_sink_rates()
1101 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_rgb()
1118 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_ycbcr444()
1156 (!drm_dp_is_branch(intel_dp->dpcd) || in intel_dp_output_format()
3425 drm_dp_enhanced_frame_cap(intel_dp->dpcd); in intel_dp_compute_config()
3547 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && in downstream_hpd_needs_d0()
3548 drm_dp_is_branch(intel_dp->dpcd) && in downstream_hpd_needs_d0()
3785 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_set_power()
[all …]
H A Dintel_psr.c509 if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { in _psr_compute_su_granularity()
547 val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; in compute_pr_dsc_support()
584 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & in _panel_replay_compute_su_granularity()
595 …w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPL… in _panel_replay_compute_su_granularity()
596 …y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ?… in _panel_replay_compute_su_granularity()
613 &connector->dp.panel_replay_caps.dpcd, in _panel_replay_init_dpcd()
614 sizeof(connector->dp.panel_replay_caps.dpcd)); in _panel_replay_init_dpcd()
618 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & in _panel_replay_init_dpcd()
629 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & in _panel_replay_init_dpcd()
640 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & in _panel_replay_init_dpcd()
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H A Dintel_dp_link_training.h16 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);
/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c536 kfree(port->dpcd); in clean_virtual_dp_monitor()
537 port->dpcd = NULL; in clean_virtual_dp_monitor()
569 port->dpcd = kzalloc_obj(*(port->dpcd)); in setup_virtual_dp_monitor()
570 if (!port->dpcd) { in setup_virtual_dp_monitor()
579 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); in setup_virtual_dp_monitor()
580 port->dpcd->data_valid = true; in setup_virtual_dp_monitor()
581 port->dpcd->data[DP_SINK_COUNT] = 0x1; in setup_virtual_dp_monitor()
H A Dhandlers.c1146 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, in dp_aux_ch_ctl_link_training() argument
1152 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CR_DONE | in dp_aux_ch_ctl_link_training()
1155 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CR_DONE | in dp_aux_ch_ctl_link_training()
1161 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CHANNEL_EQ_DONE | in dp_aux_ch_ctl_link_training()
1163 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_SYMBOL_LOCKED | in dp_aux_ch_ctl_link_training()
1166 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CHANNEL_EQ_DONE | in dp_aux_ch_ctl_link_training()
1168 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_SYMBOL_LOCKED | in dp_aux_ch_ctl_link_training()
1171 dpcd->data[DP_LANE_ALIGN_STATUS_UPDATED] |= in dp_aux_ch_ctl_link_training()
1177 dpcd->data[DP_SINK_STATUS] = DP_RECEIVE_PORT_0_STATUS | in dp_aux_ch_ctl_link_training()
1193 struct intel_vgpu_dpcd_data *dpcd = NULL; in dp_aux_ch_ctl_mmio_write() local
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-dp.c279 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
507 memset(link->dpcd, 0, sizeof(link->dpcd)); in dw_dp_link_reset()
517 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); in dw_dp_link_parse()
521 drm_dp_read_desc(&dp->aux, &link->desc, drm_dp_is_branch(link->dpcd)); in dw_dp_link_parse()
523 if (drm_dp_read_sink_count_cap(connector, link->dpcd, &link->desc)) { in dw_dp_link_parse()
535 link->vsc_sdp_supported = drm_dp_vsc_sdp_supported(&dp->aux, link->dpcd); in dw_dp_link_parse()
537 link->revision = link->dpcd[DP_DPCD_REV]; in dw_dp_link_parse()
540 drm_dp_max_link_rate(link->dpcd)); in dw_dp_link_parse()
542 drm_dp_max_lane_count(link->dpcd)); in dw_dp_link_parse()
544 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); in dw_dp_link_parse()
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dite-it6505.c452 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
653 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num) in it6505_get_dpcd() argument
658 ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num); in it6505_get_dpcd()
664 num, dpcd); in it6505_get_dpcd()
1632 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01; in it6505_use_step_train_check()
1643 if (it6505->dpcd[0] == 0) { in it6505_parse_link_capabilities()
1650 link->revision = it6505->dpcd[0]; in it6505_parse_link_capabilities()
1651 link->rate = drm_dp_bw_code_to_link_rate(it6505->dpcd[1]); in it6505_parse_link_capabilities()
1652 link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK; in it6505_parse_link_capabilities()
1654 if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP) in it6505_parse_link_capabilities()
[all …]
/linux/drivers/gpu/drm/nouveau/nvif/
H A Doutp.c113 nvif_outp_dp_train(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, in nvif_outp_dp_train()
126 memcpy(args.dpcd, dpcd, sizeof(args.dpcd)); in nvif_outp_dp_train()
148 args.rate[i].dpcd = rate->dpcd; in nvif_outp_dp_rates()
/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Doutp.h102 int dpcd; /* -1 for non-indexed rates */ member
107 int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],
H A Dif0012.h228 __s8 dpcd; member
243 __u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c406 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
787 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_cr()
835 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && in zynqmp_dp_link_train_ce()
836 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) in zynqmp_dp_link_train_ce()
852 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_ce()
950 drm_dp_enhanced_frame_cap(dp->dpcd), in zynqmp_dp_train()
951 dp->dpcd[DP_MAX_DOWNSPREAD] & in zynqmp_dp_train()
1700 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, in __zynqmp_dp_bridge_detect()
1701 sizeof(dp->dpcd)); in __zynqmp_dp_bridge_detect()
1708 drm_dp_max_link_rate(dp->dpcd), in __zynqmp_dp_bridge_detect()
[all …]
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_ctrl.c394 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_config_ctrl() local
403 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) in msm_dp_ctrl_config_ctrl()
415 if (drm_dp_enhanced_frame_cap(dpcd)) in msm_dp_ctrl_config_ctrl()
1430 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_1()
1539 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_clear_training_pattern()
1554 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_2()
1560 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1563 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1626 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_link_train() local
1639 if (drm_dp_max_downspread(dpcd)) in msm_dp_ctrl_link_train()
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/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c1331 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps()
1339 mhdp->sink.ssc = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1344 if (drm_dp_tps3_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1346 if (drm_dp_tps4_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1350 mhdp->sink.fast_link = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1356 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up() local
1372 err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE); in cdns_mhdp_link_up()
1378 mhdp->link.revision = dpcd[0]; in cdns_mhdp_link_up()
1379 mhdp->link.rate = drm_dp_bw_code_to_link_rate(dpcd[1]); in cdns_mhdp_link_up()
1380 mhdp->link.num_lanes = dpcd[2] & DP_MAX_LANE_COUNT_MASK; in cdns_mhdp_link_up()
[all …]

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