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Searched refs:dml_core_ctx (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_utils.c285 …context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCL… in dml2_calculate_rq_and_dlg_params()
288 if (in_ctx->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0] == dml_fclock_change_unsupported) in dml2_calculate_rq_and_dlg_params()
296 …context->bw_ctx.bw.dcn.compbuf_size_kb = in_ctx->v20.dml_core_ctx.ip.config_return_buffer_size_in_… in dml2_calculate_rq_and_dlg_params()
321 …ntext->res_ctx.pipe_ctx[dc_pipe_ctx_index], &context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx); in dml2_calculate_rq_and_dlg_params()
329 …er_size_kb = dml_get_det_buffer_size_kbytes(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx); in dml2_calculate_rq_and_dlg_params()
331 …context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = in_ctx->v20.dml_core_ctx.ms.Unbounded… in dml2_calculate_rq_and_dlg_params()
335 ….bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) … in dml2_calculate_rq_and_dlg_params()
339 dml_rq_dlg_get_rq_reg(&s->rq_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_idx); in dml2_calculate_rq_and_dlg_params()
340 …dml_rq_dlg_get_dlg_reg(&s->disp_dlg_regs, &s->disp_ttu_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_i… in dml2_calculate_rq_and_dlg_params()
343 …_mall_bytes = dml_get_surface_size_for_mall(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx); in dml2_calculate_rq_and_dlg_params()
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H A Ddml2_translation_helper.c36 switch (dml2->v20.dml_core_ctx.project) { in dml2_init_ip_params()
279 switch (dml2->v20.dml_core_ctx.project) { in dml2_init_socbb_params()
335 unsigned int dml_project = dml2->v20.dml_core_ctx.project; in dml2_init_soc_states()
354 switch (dml2->v20.dml_core_ctx.project) { in dml2_init_soc_states()
506 if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) || in dml2_init_soc_states()
507 (dml2->v20.dml_core_ctx.project == dml_project_dcn321)) { in dml2_init_soc_states()
513 } else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && in dml2_init_soc_states()
514 dml2->v20.dml_core_ctx.project != dml_project_dcn36 && in dml2_init_soc_states()
515 dml2->v20.dml_core_ctx.project != dml_project_dcn351) { in dml2_init_soc_states()
562 if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 || in dml2_init_soc_states()
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H A Ddml2_utils.h42 …_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx);
43 void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx);
H A Ddml2_internal_types.h39 struct display_mode_lib_st *dml_core_ctx; member
142 struct display_mode_lib_st dml_core_ctx; member
H A Ddml2_mall_phantom.c903 vstartup = dml_get_vstartup_calculated(&ctx->v20.dml_core_ctx, dml_pipe_idx); in dml2_svp_add_phantom_pipe_to_dc_state()