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Searched refs:dlg_regs (Results 1 – 25 of 38) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_rq_dlg_helpers.c180 …dlg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs) in print__dlg_regs_st() argument
186 dlg_regs->refcyc_h_blank_end); in print__dlg_regs_st()
189 dlg_regs->dlg_vblank_end); in print__dlg_regs_st()
192 dlg_regs->min_dst_y_next_start); in print__dlg_regs_st()
195 dlg_regs->refcyc_per_htotal); in print__dlg_regs_st()
198 dlg_regs->refcyc_x_after_scaler); in print__dlg_regs_st()
201 dlg_regs->dst_y_after_scaler); in print__dlg_regs_st()
204 dlg_regs->dst_y_prefetch); in print__dlg_regs_st()
207 dlg_regs->dst_y_per_vm_vblank); in print__dlg_regs_st()
210 dlg_regs->dst_y_per_row_vblank); in print__dlg_regs_st()
[all …]
H A Ddisplay_mode_lib.h53 display_dlg_regs_st *dlg_regs,
71 display_dlg_regs_st *dlg_regs,
H A Ddml1_display_rq_dlg_calc.h56 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
H A Ddisplay_rq_dlg_helpers.h42 …lg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c206 display_dlg_regs_st *dlg_regs, in dml32_rq_dlg_get_dlg_reg() argument
265 memset(dlg_regs, 0, sizeof(*dlg_regs)); in dml32_rq_dlg_get_dlg_reg()
274 dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); in dml32_rq_dlg_get_dlg_reg()
275 …dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, … in dml32_rq_dlg_get_dlg_reg()
276 dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml32_rq_dlg_get_dlg_reg()
289 dlg_regs->vready_after_vcount0 = vready_after_vcount0; in dml32_rq_dlg_get_dlg_reg()
291 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, dlg_regs->vready_after_vcount0); in dml32_rq_dlg_get_dlg_reg()
333 dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); in dml32_rq_dlg_get_dlg_reg()
340 dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end in dml32_rq_dlg_get_dlg_reg()
344 ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); in dml32_rq_dlg_get_dlg_reg()
[all …]
H A Ddisplay_rq_dlg_calc_32.h64 display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c251 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr; in dcn10_get_dlg_states() local
261 …pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_… in dcn10_get_dlg_states()
262 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler, in dcn10_get_dlg_states()
263 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank, in dcn10_get_dlg_states()
264 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, in dcn10_get_dlg_states()
265 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l, in dcn10_get_dlg_states()
266 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, in dcn10_get_dlg_states()
267 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l, in dcn10_get_dlg_states()
268 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l, in dcn10_get_dlg_states()
269 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l, in dcn10_get_dlg_states()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_util.c249 void dml_print_dlg_regs_st(const dml_display_dlg_regs_st *dlg_regs) in dml_print_dlg_regs_st() argument
253 dml_print("DML: refcyc_h_blank_end = 0x%x\n", dlg_regs->refcyc_h_blank_end); in dml_print_dlg_regs_st()
254 dml_print("DML: dlg_vblank_end = 0x%x\n", dlg_regs->dlg_vblank_end); in dml_print_dlg_regs_st()
255 dml_print("DML: min_dst_y_next_start = 0x%x\n", dlg_regs->min_dst_y_next_start); in dml_print_dlg_regs_st()
256 dml_print("DML: refcyc_per_htotal = 0x%x\n", dlg_regs->refcyc_per_htotal); in dml_print_dlg_regs_st()
257 dml_print("DML: refcyc_x_after_scaler = 0x%x\n", dlg_regs->refcyc_x_after_scaler); in dml_print_dlg_regs_st()
258 dml_print("DML: dst_y_after_scaler = 0x%x\n", dlg_regs->dst_y_after_scaler); in dml_print_dlg_regs_st()
259 dml_print("DML: dst_y_prefetch = 0x%x\n", dlg_regs->dst_y_prefetch); in dml_print_dlg_regs_st()
260 dml_print("DML: dst_y_per_vm_vblank = 0x%x\n", dlg_regs->dst_y_per_vm_vblank); in dml_print_dlg_regs_st()
261 dml_print("DML: dst_y_per_row_vblank = 0x%x\n", dlg_regs->dst_y_per_row_vblank); in dml_print_dlg_regs_st()
[all …]
H A Ddml2_translation_helper.c1459 memset(&out->dlg_regs, 0, sizeof(out->dlg_regs)); in dml2_update_pipe_ctx_dchub_regs()
1460 out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end; in dml2_update_pipe_ctx_dchub_regs()
1461 out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end; in dml2_update_pipe_ctx_dchub_regs()
1462 out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start; in dml2_update_pipe_ctx_dchub_regs()
1463 out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal; in dml2_update_pipe_ctx_dchub_regs()
1464 out->dlg_regs.refcyc_x_after_scaler = disp_dlg_regs->refcyc_x_after_scaler; in dml2_update_pipe_ctx_dchub_regs()
1465 out->dlg_regs.dst_y_after_scaler = disp_dlg_regs->dst_y_after_scaler; in dml2_update_pipe_ctx_dchub_regs()
1466 out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch; in dml2_update_pipe_ctx_dchub_regs()
1467 out->dlg_regs.dst_y_per_vm_vblank = disp_dlg_regs->dst_y_per_vm_vblank; in dml2_update_pipe_ctx_dchub_regs()
1468 out->dlg_regs.dst_y_per_row_vblank = disp_dlg_regs->dst_y_per_row_vblank; in dml2_update_pipe_ctx_dchub_regs()
[all …]
H A Ddml_display_rq_dlg_calc.h55 void dml_rq_dlg_get_dlg_reg(dml_display_dlg_regs_st *dlg_regs,
H A Ddisplay_mode_util.h55 __DML_DLL_EXPORT__ void dml_print_dlg_regs_st(const dml_display_dlg_regs_st *dlg_regs);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c341 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr; in dcn10_log_hubp_states() local
362 dlg_regs->dst_y_prefetch}; in dcn10_log_hubp_states()
403 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr; in dcn10_log_hubp_states() local
409 …pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_… in dcn10_log_hubp_states()
410 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler, in dcn10_log_hubp_states()
411 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank, in dcn10_log_hubp_states()
412 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, in dcn10_log_hubp_states()
413 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l, in dcn10_log_hubp_states()
414 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, in dcn10_log_hubp_states()
415 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l, in dcn10_log_hubp_states()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c357 hubp401_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs); in hubp401_setup()
367 DST_Y_PREFETCH, pipe_regs->dlg_regs.dst_y_prefetch, in hubp401_setup_interdependent()
368 VRATIO_PREFETCH, pipe_regs->dlg_regs.vratio_prefetch); in hubp401_setup_interdependent()
371 VRATIO_PREFETCH_C, pipe_regs->dlg_regs.vratio_prefetch_c); in hubp401_setup_interdependent()
374 DST_Y_PER_VM_VBLANK, pipe_regs->dlg_regs.dst_y_per_vm_vblank, in hubp401_setup_interdependent()
375 DST_Y_PER_ROW_VBLANK, pipe_regs->dlg_regs.dst_y_per_row_vblank); in hubp401_setup_interdependent()
378 DST_Y_PER_VM_FLIP, pipe_regs->dlg_regs.dst_y_per_vm_flip, in hubp401_setup_interdependent()
379 DST_Y_PER_ROW_FLIP, pipe_regs->dlg_regs.dst_y_per_row_flip); in hubp401_setup_interdependent()
382 REFCYC_PER_META_CHUNK_VBLANK_L, pipe_regs->dlg_regs.refcyc_per_meta_chunk_vblank_l); in hubp401_setup_interdependent()
385 REFCYC_PER_META_CHUNK_VBLANK_C, pipe_regs->dlg_regs.refcyc_per_meta_chunk_vblank_c); in hubp401_setup_interdependent()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.h59 display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.h62 display_dlg_regs_st *dlg_regs,
H A Ddisplay_rq_dlg_calc_20v2.h62 display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.h58 display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.h58 display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.h62 display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dhubp.h161 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
174 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
H A Dmem_input.h107 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/
H A Ddml_top_dchub_registers.h151 struct dml2_display_dlg_regs dlg_regs; member
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c2974 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_params.dlg_regs; in hwss_hubp_setup() local
2980 hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest); in hwss_hubp_setup()
3004 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_interdependent_params.dlg_regs; in hwss_hubp_setup_interdependent() local
3008 hubp->funcs->hubp_setup_interdependent(hubp, dlg_regs, ttu_regs); in hwss_hubp_setup_interdependent()
3823 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, in hwss_add_hubp_setup() argument
3831 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.dlg_regs = dlg_regs; in hwss_add_hubp_setup()
3865 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, in hwss_add_hubp_setup_interdependent() argument
3871 …eq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.dlg_regs = dlg_regs; in hwss_add_hubp_setup_interdependent()
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h650 struct _vcs_dpi_display_dlg_regs_st *dlg_regs; member
668 struct _vcs_dpi_display_dlg_regs_st *dlg_regs; member
1924 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
1939 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c459 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs; in dcn_bw_calc_rq_dlg_ttu() local
470 memset(dlg_regs, 0, sizeof(*dlg_regs)); in dcn_bw_calc_rq_dlg_ttu()
511 dlg_regs, in dcn_bw_calc_rq_dlg_ttu()

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