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Searched refs:dkl (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_dkl_phy.c20 spin_lock_init(&display->dkl.phy_lock); in intel_dkl_phy_init()
51 spin_lock(&display->dkl.phy_lock); in intel_dkl_phy_read()
56 spin_unlock(&display->dkl.phy_lock); in intel_dkl_phy_read()
72 spin_lock(&display->dkl.phy_lock); in intel_dkl_phy_write()
77 spin_unlock(&display->dkl.phy_lock); in intel_dkl_phy_write()
93 spin_lock(&display->dkl.phy_lock); in intel_dkl_phy_rmw()
98 spin_unlock(&display->dkl.phy_lock); in intel_dkl_phy_rmw()
111 spin_lock(&display->dkl.phy_lock); in intel_dkl_phy_posting_read()
116 spin_unlock(&display->dkl.phy_lock); in intel_dkl_phy_posting_read()
H A Dintel_ddi_buf_trans.c653 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */
654 { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */
655 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */
656 { .dkl = { 0x0, 0x0, 0x18 } }, /* 0 3 400mV 9.5 dB */
657 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */
658 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */
659 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */
660 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */
661 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */
662 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */
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H A Dintel_ddi_buf_trans.h66 struct tgl_dkl_phy_ddi_buf_trans dkl; member