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Searched refs:divider_get_val (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/clk/meson/
H A Dclk-cpu-dyndiv.c47 ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0); in meson_clk_cpu_dyndiv_set_rate()
H A Dvclk.c90 ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width, in meson_vclk_div_set_rate()
H A Dclk-regmap.c156 ret = divider_get_val(rate, parent_rate, div->table, div->width, in clk_regmap_div_set_rate()
/linux/drivers/clk/
H A Dclk-divider.c455 int divider_get_val(unsigned long rate, unsigned long parent_rate, in divider_get_val() function
470 EXPORT_SYMBOL_GPL(divider_get_val);
480 value = divider_get_val(rate, parent_rate, divider->table, in clk_divider_set_rate()
H A Dclk-milbeaut.c418 value = divider_get_val(rate, parent_rate, divider->table, in m10v_clk_divider_set_rate()
H A Dclk-bm1880.c641 value = divider_get_val(rate, parent_rate, div->table, in bm1880_clk_div_set_rate()
/linux/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c75 value = divider_get_val(rate, parent_rate, dclk->table, in hi6220_clkdiv_set_rate()
/linux/drivers/clk/imx/
H A Dclk-divider-gate.c82 value = divider_get_val(rate, parent_rate, div->table, in clk_divider_gate_set_rate()
H A Dclk-composite-93.c116 value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags); in imx93_clk_composite_divider_set_rate()
/linux/drivers/clk/microchip/
H A Dclk-mpfs.c281 divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); in mpfs_cfg_clk_set_rate()
/linux/include/linux/
H A Dclk-provider.h756 int divider_get_val(unsigned long rate, unsigned long parent_rate,
/linux/drivers/clk/sophgo/
H A Dclk-sg2044.c183 value = divider_get_val(rate, parent_rate, NULL, in sg2044_div_set_rate()
/linux/drivers/phy/ti/
H A Dphy-j721e-wiz.c953 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); in wiz_clk_div_set_rate()