Searched refs:div_ctl0 (Results 1 – 1 of 1) sorted by relevance
364 u32 gnrl_ctl, div_ctl0; in clk_pll1443x_set_rate() local369 div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); in clk_pll1443x_set_rate()371 if (!clk_pll14xx_mp_change(&rate, div_ctl0)) { in clk_pll1443x_set_rate()373 div_ctl0 &= ~SDIV_MASK; in clk_pll1443x_set_rate()374 div_ctl0 |= FIELD_PREP(SDIV_MASK, rate.sdiv); in clk_pll1443x_set_rate()375 writel_relaxed(div_ctl0, pll->base + DIV_CTL0); in clk_pll1443x_set_rate()392 div_ctl0 = FIELD_PREP(MDIV_MASK, rate.mdiv) | in clk_pll1443x_set_rate()395 writel_relaxed(div_ctl0, pll->base + DIV_CTL0); in clk_pll1443x_set_rate()