| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 157 static void get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg) in get_stream_output_bpp() argument
159 for (unsigned int k = 0; k < display_cfg->num_planes; k++) { in get_stream_output_bpp()
160 …double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in get_stream_output_bpp()
161 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in get_stream_output_bpp()
162 …switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.out… in get_stream_output_bpp()
177 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in get_stream_output_bpp()
178 …out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in get_stream_output_bpp()
183 …_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg… in get_stream_output_bpp()
245 static bool dml_get_is_phantom_pipe(const struct dml2_display_cfg *display_cfg, const struct dml2_c… in dml_get_is_phantom_pipe() argument
249 bool is_phantom = dml_is_phantom_pipe(&display_cfg->plane_descriptors[plane_idx]); in dml_get_is_phantom_pipe()
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| H A D | dml2_core_utils.c | 337 … dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg) in dml2_core_utils_get_stream_output_bpp() argument
339 for (unsigned int k = 0; k < display_cfg->num_planes; k++) { in dml2_core_utils_get_stream_output_bpp()
340 …double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
341 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in dml2_core_utils_get_stream_output_bpp()
342 …switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.out… in dml2_core_utils_get_stream_output_bpp()
357 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in dml2_core_utils_get_stream_output_bpp()
358 …out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
364 …_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg… in dml2_core_utils_get_stream_output_bpp()
610 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,… in dml2_core_utils_expand_implict_subvp() argument
618 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in dml2_core_utils_expand_implict_subvp()
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| H A D | dml2_core_dcn4.c | 190 static void expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct d… in expand_implict_subvp() argument
198 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in expand_implict_subvp()
203 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in expand_implict_subvp()
207 if (!display_cfg->stage3.performed) { in expand_implict_subvp()
212 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in expand_implict_subvp()
213 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in expand_implict_subvp()
217 if (display_cfg->stage3.stream_svp_meta[stream_index].valid) { in expand_implict_subvp()
220 main_stream, &display_cfg->stage3.stream_svp_meta[stream_index]); in expand_implict_subvp()
232 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in expand_implict_subvp()
233 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in expand_implict_subvp()
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| H A D | dml2_core_dcn4_calcs.h | 21 void dml2_core_calcs_get_watermarks(const struct dml2_display_cfg *display_cfg, const struct dml2_c…
22 void dml2_core_calcs_get_arb_params(const struct dml2_display_cfg *display_cfg, const struct dml2_c…
27 void dml2_core_calcs_get_plane_support_info(const struct dml2_display_cfg *display_cfg, const struc…
29 void dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg *display_cfg, const stru…
31 …splay_mode_lib *mode_lib, const struct display_configuation_with_meta *display_cfg, union dmub_cmd…
32 …splay_mode_lib *mode_lib, const struct display_configuation_with_meta *display_cfg, struct dmub_cm…
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| H A D | dml2_core_utils.h | 18 …dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);
32 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,…
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/ |
| H A D | dml2_dpmm_dcn4.c | 39 if (in_out->display_cfg->stage3.success) in get_minimum_clocks_for_latency()
40 min_clock_index_for_latency = in_out->display_cfg->stage3.min_clk_index_for_latency; in get_minimum_clocks_for_latency()
42 min_clock_index_for_latency = in_out->display_cfg->stage1.min_clk_index_for_latency; in get_minimum_clocks_for_latency()
64 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_system_active_minimums()
70 if (in_out->display_cfg->display_config.hostvm_enable) in calculate_system_active_minimums()
111 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_svp_prefetch_minimums()
186 …const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_suppo… in calculate_idle_minimums()
302 static bool map_soc_min_clocks_to_dpm_fine_grained(struct dml2_display_cfg_programming *display_cfg… in map_soc_min_clocks_to_dpm_fine_grained() argument
306 …result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.dcfclk_khz, &state_table->dcfc… in map_soc_min_clocks_to_dpm_fine_grained()
308 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.fclk_khz, &state_table->fclk); in map_soc_min_clocks_to_dpm_fine_grained()
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| /linux/drivers/gpu/drm/amd/pm/ |
| H A D | amdgpu_dpm_internal.c | 34 struct single_display_configuration *display_cfg; in amdgpu_dpm_get_display_cfg() local
53 display_cfg = &adev->pm.pm_display_cfg.displays[num_crtcs++]; in amdgpu_dpm_get_display_cfg()
88 display_cfg->controller_id = amdgpu_crtc->crtc_id; in amdgpu_dpm_get_display_cfg()
89 display_cfg->pixel_clock = conn->pixelclock_for_modeset; in amdgpu_dpm_get_display_cfg()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/ |
| H A D | dml2_pmo_dcn4_fams2.c | 231 static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int … in count_planes_with_stream_index() argument
236 for (i = 0; i < display_cfg->num_planes; i++) { in count_planes_with_stream_index()
237 if (display_cfg->plane_descriptors[i].stream_index == stream_index) in count_planes_with_stream_index()
1242 static bool all_planes_match_method(const struct display_configuation_with_meta *display_cfg, int p… in all_planes_match_method() argument
1248 …if (display_cfg->display_config.plane_descriptors[i].overrides.uclk_pstate_change_strategy != dml2… in all_planes_match_method()
1249 …display_cfg->display_config.plane_descriptors[i].overrides.uclk_pstate_change_strategy != pstate_m… in all_planes_match_method()
1311 const struct display_configuation_with_meta *display_cfg, in is_timing_group_schedulable() argument
1323 …for (base_stream_idx = 0; base_stream_idx < display_cfg->display_config.num_streams; base_stream_i… in is_timing_group_schedulable()
1338 for (i = base_stream_idx + 1; i < display_cfg->display_config.num_streams; i++) { in is_timing_group_schedulable()
1371 const struct display_configuation_with_meta *display_cfg, in is_config_schedulable() argument
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| H A D | dml2_pmo_dcn3.c | 184 static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int … in count_planes_with_stream_index() argument
189 for (i = 0; i < display_cfg->num_planes; i++) { in count_planes_with_stream_index()
190 if (display_cfg->plane_descriptors[i].stream_index == stream_index) in count_planes_with_stream_index()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/ |
| H A D | dml2_internal_shared_types.h | 87 const struct display_configuation_with_meta *display_cfg; member
103 const struct display_configuation_with_meta *display_cfg; member
387 const struct display_configuation_with_meta *display_cfg; member
398 struct dml_display_cfg_st *display_cfg; member
418 const struct display_configuation_with_meta *display_cfg; member
767 const struct dml2_display_cfg *display_cfg; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/ |
| H A D | dml2_top_soc15.c | 79 …l->test_mcache.validate_admissibility_params.display_cfg = ¶ms->display_config->display_config; in dml2_top_optimization_test_function_mcache()
250 l->mode_support_params.display_cfg = &l->next_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase()
302 l->mode_support_params.display_cfg = &l->cur_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase_1()
531 for (plane_index = 0; plane_index < params->display_cfg->num_planes; plane_index++) { in dml2_top_mcache_validate_admissability()
532 if (!params->display_cfg->plane_descriptors[plane_index].surface.dcc.enable) in dml2_top_mcache_validate_admissability()
535 plane = ¶ms->display_cfg->plane_descriptors[plane_index]; in dml2_top_mcache_validate_admissability()
536 stream = ¶ms->display_cfg->stream_descriptors[plane->stream_index]; in dml2_top_mcache_validate_admissability()
788 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_check_mode_supported()
811 l->dppm_map_mode_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_check_mode_supported()
843 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | display_mode_util.h | 68 …ML_DLL_EXPORT__ dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg);
69 __DML_DLL_EXPORT__ dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg…
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| H A D | display_mode_core.h | 67 const struct dml_display_cfg_st *display_cfg);
72 const struct dml_display_cfg_st *display_cfg,
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| H A D | display_mode_util.c | 728 dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg) in dml_get_num_active_planes() argument
733 if (display_cfg->plane.ViewportWidth[k] > 0) in dml_get_num_active_planes()
743 dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg) in dml_get_num_active_pipes() argument
747 for (dml_uint_t j = 0; j < dml_get_num_active_planes(display_cfg); j++) { in dml_get_num_active_pipes()
748 num_active_pipes = num_active_pipes + display_cfg->hw.DPPPerSurface[j]; in dml_get_num_active_pipes()
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| H A D | display_mode_core.c | 372 …lockAdjustmentForProgressiveToInterlaceUnit(struct dml_display_cfg_st *display_cfg, dml_bool_t pto…
2693 …lockAdjustmentForProgressiveToInterlaceUnit(struct dml_display_cfg_st *display_cfg, dml_bool_t pto… in PixelClockAdjustmentForProgressiveToInterlaceUnit() argument
2695 dml_uint_t num_active_planes = dml_get_num_active_planes(display_cfg); in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2699 display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2700 if (display_cfg->timing.Interlace[k] == 1 && ptoi_supported == true) { in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2701 display_cfg->timing.PixelClock[k] = 2 * display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
10073 const struct dml_display_cfg_st *display_cfg) in cache_display_cfg() argument
10075 mode_lib->ms.cache_display_cfg = *display_cfg; in cache_display_cfg()
10101 const struct dml_display_cfg_st *display_cfg) in dml_mode_support() argument
10107 cache_display_cfg(mode_lib, display_cfg); in dml_mode_support()
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | si_dpm.c | 3441 const struct amd_pp_display_configuration *display_cfg = in si_apply_state_adjust_rules() local
3495 for (i = 0; i < display_cfg->num_display; i++) { in si_apply_state_adjust_rules()
3497 if (display_cfg->displays[i].pixel_clock > 297000) in si_apply_state_adjust_rules()
3678 display_cfg->display_clk, in si_apply_state_adjust_rules()
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