| /linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/ |
| H A D | dcn401_soc_and_ip_translator.c | 114 dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
116 if (i < dml_clk_table->dispclk.num_clk_values) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
120 dml_clk_table->dispclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dispclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
121 dml_clk_table->dispclk.num_clk_values = i + 1; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
123 dml_clk_table->dispclk.clk_values_khz[i] = 0; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
124 dml_clk_table->dispclk.num_clk_values = i; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
127 dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
130 dml_clk_table->dispclk.clk_values_khz[i] = 0; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/ |
| H A D | dml2_mcg_dcn4.c | 179 …min_table->max_clocks_khz.dispclk = soc_bb->clk_table.dispclk.clk_values_khz[soc_bb->clk_table.dis… in build_min_clock_table()
185 …min_table->max_ss_clocks_khz.dispclk = (unsigned int)((double)min_table->max_clocks_khz.dispclk / … in build_min_clock_table()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_wrapper.c | 153 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
155 …in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table… in dml21_calculate_rq_and_dlg_params()
157 …cn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0]… in dml21_calculate_rq_and_dlg_params()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | atombios_crtc.h | 39 u32 dispclk);
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| H A D | atombios_crtc.c | 471 u32 dispclk) in amdgpu_atombios_crtc_set_disp_eng_pll() argument
492 args.v5.usPixelClock = cpu_to_le16(dispclk); in amdgpu_atombios_crtc_set_disp_eng_pll()
499 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); in amdgpu_atombios_crtc_set_disp_eng_pll()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/ |
| H A D | dml_top_soc_parameter_types.h | 127 struct dml2_clk_table dispclk; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/ |
| H A D | dcn4_soc_bb.h | 97 .dispclk = {
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/ |
| H A D | dml2_internal_shared_types.h | 32 unsigned int dispclk; member
42 unsigned int dispclk; member
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 188 uint32_t dispclk; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 361 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn401_dump_clk_registers()
508 clk_register_dump.dispclk, in dcn401_auto_dpm_test_log()
1105 clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk; in dcn401_build_update_display_clocks_sequence()
1510 clk_mgr->base.boot_snapshot.dispclk; in dcn401_get_max_clock_khz()
1520 clk_mgr->base.boot_snapshot.dispclk / 3; in dcn401_get_max_clock_khz()
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| /linux/drivers/gpu/drm/amd/display/dc/basics/ |
| H A D | dce_calcs.c | 1751 data->dispclk = data->total_dispclk_required_with_ramping_with_request_bandwidth; in calculate_bandwidth()
1754 data->dispclk = vbios->high_voltage_max_dispclk; in calculate_bandwidth()
1757 data->dispclk = data->total_dispclk_required_without_ramping_with_request_bandwidth; in calculate_bandwidth()
1770 …message), vbios->low_yclk) && sclk_message == bw_def_low && bw_ltn(data->dispclk, vbios->low_volta… in calculate_bandwidth()
1773 …clk_message == bw_def_low || sclk_message == bw_def_mid) && bw_ltn(data->dispclk, vbios->mid_volta… in calculate_bandwidth()
1776 …lk_message == bw_def_mid || sclk_message == bw_def_high) && bw_leq(data->dispclk, vbios->high_volt… in calculate_bandwidth()
1803 …dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), d… in calculate_bandwidth()
1809 …dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), d… in calculate_bandwidth()
1844 …data->sclk_deep_sleep = bw_max2(bw_div(bw_mul(data->dispclk, bw_frc_to_fixed(115, 100)), data->min… in calculate_bandwidth()
1856 …ful_bytes_per_request[i])), bw_min2(sclk[data->sclk_level], bw_div(data->dispclk, bw_int_to_fixed(… in calculate_bandwidth()
[all …]
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| H A D | calcs_logger.h | 332 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk: %d", bw_fixed_to_int(data->dispclk)); in print_bw_calcs_data()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 319 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; in rn_dump_clk_registers()
358 regs_and_bypass->dispclk, in rn_dump_clk_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 251 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; in vg_dump_clk_registers()
290 regs_and_bypass->dispclk, in vg_dump_clk_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 631 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; in dcn35_save_clk_registers()
662 regs_and_bypass->dispclk, in dcn35_save_clk_registers()
1307 clk_mgr->base.boot_snapshot.dispclk; in dcn35_get_max_clock_khz()
1317 clk_mgr->base.boot_snapshot.dispclk / 3; in dcn35_get_max_clock_khz()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | dce_calcs.h | 332 struct bw_fixed dispclk; member
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| H A D | dcn_calcs.h | 435 float dispclk; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/ |
| H A D | dml2_dpmm_dcn4.c | 409 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.dispclk_khz, &state_table->dispclk); in map_min_clocks_to_dpm()
633 dispclk_khz = math_min2(dispclk_khz, in_out->min_clk_table->max_clocks_khz.dispclk); in map_mode_to_soc_dpm()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calc_auto.c | 1215 v->dispclk = v->dispclk_without_ramping; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1218 v->dispclk = v->max_dispclk[number_of_states]; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1221 v->dispclk = v->dispclk_with_ramping; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1643 …->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1654 …total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
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| H A D | dcn_calcs.c | 495 input->clks_cfg.dispclk_mhz = v->dispclk; in dcn_bw_calc_rq_dlg_ttu()
1165 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000); in dcn_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 910 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn32_dump_clk_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 78 clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000; in dcn401_initialize_min_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 3509 double dispclk, in CalculateDCFCLKDeepSleepTdlut() argument
3559 DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], dispclk / 4.0); in CalculateDCFCLKDeepSleepTdlut()
7975 mode_lib->ms.max_dispclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dispclk / 1000; in dml_core_mode_support()
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