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Searched refs:disp_int (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Drs600.c726 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); in rs600_irq_ack()
727 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
731 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
735 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
740 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
746 rdev->irq.stat_regs.r500.disp_int = 0; in rs600_irq_ack()
786 !rdev->irq.stat_regs.r500.disp_int && in rs600_irq_process()
791 rdev->irq.stat_regs.r500.disp_int || in rs600_irq_process()
798 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
807 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
[all …]
H A Dr600.c3917 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3928 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3941 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3943 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3945 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3947 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3949 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3960 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
4135 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) in r600_irq_process()
4145 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
[all …]
H A Dsi.c6128 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in si_irq_ack() local
6135 disp_int[i] = RREG32(si_disp_int_status[i]); in si_irq_ack()
6149 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT) in si_irq_ack()
6152 if (disp_int[j] & LB_D1_VLINE_INTERRUPT) in si_irq_ack()
6159 if (disp_int[i] & DC_HPD1_INTERRUPT) in si_irq_ack()
6164 if (disp_int[i] & DC_HPD1_RX_INTERRUPT) in si_irq_ack()
6227 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in si_irq_process() local
6298 if (!(disp_int[crtc_idx] & mask)) { in si_irq_process()
6303 disp_int[crtc_idx] &= ~mask; in si_irq_process()
6336 if (!(disp_int[hpd_idx] & mask)) in si_irq_process()
[all …]
H A Dcik.c7289 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS); in cik_irq_ack()
7320 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) in cik_irq_ack()
7322 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) in cik_irq_ack()
7363 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) { in cik_irq_ack()
7393 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) { in cik_irq_ack()
7584 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)) in cik_irq_process()
7594 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in cik_irq_process()
7599 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)) in cik_irq_process()
7602 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT; in cik_irq_process()
7774 if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT)) in cik_irq_process()
[all …]
H A Dradeon.h707 u32 disp_int; member
712 u32 disp_int; member
722 u32 disp_int[6]; member
728 u32 disp_int; member
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c3088 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq() local
3094 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()
3105 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()
3200 uint32_t disp_int, mask; in dce_v8_0_hpd_irq() local
3209 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()
3212 if (disp_int & mask) { in dce_v8_0_hpd_irq()
H A Ddce_v6_0.c3072 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq() local
3078 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()
3089 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()
3184 uint32_t disp_int, mask; in dce_v6_0_hpd_irq() local
3193 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()
3196 if (disp_int & mask) { in dce_v6_0_hpd_irq()
H A Ddce_v10_0.c3255 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq() local
3260 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()
3272 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()
3292 uint32_t disp_int, mask; in dce_v10_0_hpd_irq() local
3301 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3304 if (disp_int & mask) { in dce_v10_0_hpd_irq()