| /linux/drivers/gpu/drm/amd/amdgpu/ ! |
| H A D | dce_v8_0.c | 652 u32 disp_clk; /* display clock in kHz */ member
764 fixed20_12 disp_clk, bandwidth; in dce_v8_0_dmif_request_bandwidth() local
768 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v8_0_dmif_request_bandwidth()
769 disp_clk.full = dfixed_div(disp_clk, a); in dce_v8_0_dmif_request_bandwidth()
771 b.full = dfixed_mul(a, disp_clk); in dce_v8_0_dmif_request_bandwidth()
850 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v8_0_latency_watermark()
874 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v8_0_latency_watermark()
877 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v8_0_latency_watermark()
1008 wm_high.disp_clk = mode->clock; in dce_v8_0_program_watermarks()
1047 wm_low.disp_clk = mode->clock; in dce_v8_0_program_watermarks()
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| H A D | dce_v6_0.c | 552 u32 disp_clk; /* display clock in kHz */ member
664 fixed20_12 disp_clk, bandwidth; in dce_v6_0_dmif_request_bandwidth() local
668 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v6_0_dmif_request_bandwidth()
669 disp_clk.full = dfixed_div(disp_clk, a); in dce_v6_0_dmif_request_bandwidth()
671 b.full = dfixed_mul(a, disp_clk); in dce_v6_0_dmif_request_bandwidth()
750 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v6_0_latency_watermark()
774 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v6_0_latency_watermark()
777 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v6_0_latency_watermark()
917 wm_high.disp_clk = mode->clock; in dce_v6_0_program_watermarks()
944 wm_low.disp_clk = mode->clock; in dce_v6_0_program_watermarks()
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| H A D | dce_v10_0.c | 699 u32 disp_clk; /* display clock in kHz */ member
811 fixed20_12 disp_clk, bandwidth; in dce_v10_0_dmif_request_bandwidth() local
815 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v10_0_dmif_request_bandwidth()
816 disp_clk.full = dfixed_div(disp_clk, a); in dce_v10_0_dmif_request_bandwidth()
818 b.full = dfixed_mul(a, disp_clk); in dce_v10_0_dmif_request_bandwidth()
897 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v10_0_latency_watermark()
921 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v10_0_latency_watermark()
924 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v10_0_latency_watermark()
1055 wm_high.disp_clk = mode->clock; in dce_v10_0_program_watermarks()
1094 wm_low.disp_clk = mode->clock; in dce_v10_0_program_watermarks()
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| /linux/drivers/gpu/drm/vc4/ ! |
| H A D | vc4_hvs.c | 1686 hvs->disp_clk = devm_clk_get(&pdev->dev, in vc4_hvs_bind()
1688 if (IS_ERR(hvs->disp_clk)) { in vc4_hvs_bind()
1690 return PTR_ERR(hvs->disp_clk); in vc4_hvs_bind()
1710 ret = clk_prepare_enable(hvs->disp_clk); in vc4_hvs_bind()
1772 clk_disable_unprepare(hvs->disp_clk); in vc4_hvs_unbind()
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| H A D | vc4_kms.c | 443 WARN_ON(clk_set_min_rate(hvs->disp_clk, core_rate)); in vc4_atomic_commit_tail()
495 WARN_ON(clk_set_min_rate(hvs->disp_clk, core_rate)); in vc4_atomic_commit_tail()
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| H A D | vc4_drv.h | 323 struct clk *disp_clk; member
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| /linux/drivers/gpu/drm/radeon/ ! |
| H A D | si.c | 2037 u32 disp_clk; /* display clock in kHz */ member
2118 fixed20_12 disp_clk, sclk, bandwidth; in dce6_dmif_request_bandwidth() local
2123 disp_clk.full = dfixed_const(wm->disp_clk); in dce6_dmif_request_bandwidth()
2124 disp_clk.full = dfixed_div(disp_clk, a); in dce6_dmif_request_bandwidth()
2126 b1.full = dfixed_mul(a, disp_clk); in dce6_dmif_request_bandwidth()
2187 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce6_latency_watermark()
2211 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce6_latency_watermark()
2214 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce6_latency_watermark()
2315 wm_high.disp_clk = mode->clock; in dce6_program_watermarks()
2342 wm_low.disp_clk = mode->clock; in dce6_program_watermarks()
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| H A D | cik.c | 8920 u32 disp_clk; /* display clock in kHz */ member
9032 fixed20_12 disp_clk, bandwidth; in dce8_dmif_request_bandwidth() local
9036 disp_clk.full = dfixed_const(wm->disp_clk); in dce8_dmif_request_bandwidth()
9037 disp_clk.full = dfixed_div(disp_clk, a); in dce8_dmif_request_bandwidth()
9039 b.full = dfixed_mul(a, disp_clk); in dce8_dmif_request_bandwidth()
9118 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce8_latency_watermark()
9142 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce8_latency_watermark()
9145 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce8_latency_watermark()
9277 wm_high.disp_clk = mode->clock; in dce8_program_watermarks()
9317 wm_low.disp_clk = mode->clock; in dce8_program_watermarks()
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| H A D | trinity_dpm.c | 1590 u64 disp_clk = rdev->clock.default_dispclk / 100; in trinity_add_dccac_value() local
1596 dc_cac_value = (u32)((14213 * disp_clk * disp_clk * (u64)num_active_displays) >> in trinity_add_dccac_value()
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| /linux/arch/arm64/boot/dts/sprd/ ! |
| H A D | whale2.dtsi | 73 clocks = <&disp_clk 0>;
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| H A D | sc9860.dtsi | 232 disp_clk: clock-controller@63000000 { label
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| /linux/arch/arm/boot/dts/ti/omap/ ! |
| H A D | am43xx-clocks.dtsi | 624 disp_clk: clock-disp@4244 { label
627 clock-output-names = "disp_clk";
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| H A D | am437x-l4.dtsi | 2166 clocks = <&disp_clk>;
2203 clocks = <&disp_clk>;
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