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Searched refs:dcn_reg_offsets (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn36.c11 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
H A Ddmub_dcn351.c11 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c166 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn36/
H A Dirq_service_dcn36.c144 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c145 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c114 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
199 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
1111 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_types.h827 uint32_t *dcn_reg_offsets; member
H A Ddc.h1270 uint32_t *dcn_reg_offsets; member
1804 uint32_t *dcn_reg_offsets; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c95 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
186 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
1107 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c114 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
200 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
1130 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c1021 dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets; in dc_construct_ctx()
1532 dc->dcn_reg_offsets = init_params->dcn_reg_offsets; in dc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c113 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c128 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c108 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c1980 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; in amdgpu_dm_init()