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Searched refs:dcn3_16_soc (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c364 static struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = { variable
739 memcpy(s, dcn3_16_soc.clock_limits, sizeof(dcn3_16_soc.clock_limits)); in dcn316_update_bw_bounding_box()
744 dcn3_16_soc.num_chans = bw_params->num_channels; in dcn316_update_bw_bounding_box()
758 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { in dcn316_update_bw_bounding_box()
759 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= in dcn316_update_bw_bounding_box()
777 dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn316_update_bw_bounding_box()
780 dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn316_update_bw_bounding_box()
783 dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; in dcn316_update_bw_bounding_box()
784 s[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn316_update_bw_bounding_box()
785 s[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn316_update_bw_bounding_box()
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