1 /* SPDX-License-Identifier: MIT */
2 /* Copyright 2024 Advanced Micro Devices, Inc. */
3
4
5 #include "dm_services.h"
6 #include "dc.h"
7
8 #include "dcn31/dcn31_init.h"
9 #include "dcn351/dcn351_init.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "dcn351_resource.h"
14
15 #include "dcn20/dcn20_resource.h"
16 #include "dcn30/dcn30_resource.h"
17 #include "dcn31/dcn31_resource.h"
18 #include "dcn32/dcn32_resource.h"
19 #include "dcn35/dcn35_resource.h"
20
21 #include "dcn10/dcn10_ipp.h"
22 #include "dcn30/dcn30_hubbub.h"
23 #include "dcn31/dcn31_hubbub.h"
24 #include "dcn35/dcn35_hubbub.h"
25 #include "dcn32/dcn32_mpc.h"
26 #include "dcn35/dcn35_hubp.h"
27 #include "irq/dcn351/irq_service_dcn351.h"
28 #include "dcn35/dcn35_dpp.h"
29 #include "dcn35/dcn35_optc.h"
30 #include "dcn20/dcn20_hwseq.h"
31 #include "dcn30/dcn30_hwseq.h"
32 #include "dce110/dce110_hwseq.h"
33 #include "dcn35/dcn35_opp.h"
34 #include "dcn35/dcn35_dsc.h"
35 #include "dcn30/dcn30_vpg.h"
36 #include "dcn30/dcn30_afmt.h"
37
38 #include "dcn31/dcn31_dio_link_encoder.h"
39 #include "dcn35/dcn35_dio_stream_encoder.h"
40 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
41 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
42 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
43 #include "link_service.h"
44 #include "dcn31/dcn31_apg.h"
45 #include "dcn32/dcn32_dio_link_encoder.h"
46 #include "dcn31/dcn31_vpg.h"
47 #include "dcn31/dcn31_afmt.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_hwseq.h"
51 #include "clk_mgr.h"
52 #include "dio/virtual/virtual_stream_encoder.h"
53 #include "dio/dcn10/dcn10_dio.h"
54 #include "dce110/dce110_resource.h"
55 #include "dml/display_mode_vba.h"
56 #include "dcn35/dcn35_dccg.h"
57 #include "dcn35/dcn35_pg_cntl.h"
58 #include "dcn10/dcn10_resource.h"
59 #include "dcn31/dcn31_panel_cntl.h"
60 #include "dcn35/dcn35_hwseq.h"
61 #include "dcn35/dcn35_dio_link_encoder.h"
62 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
63 #include "dml/dcn35/dcn35_fpu.h"
64 #include "dml/dcn351/dcn351_fpu.h"
65 #include "dcn35/dcn35_dwb.h"
66 #include "dcn35/dcn35_mmhubbub.h"
67
68 #include "dcn/dcn_3_5_1_offset.h"
69 #include "dcn/dcn_3_5_1_sh_mask.h"
70 #include "nbio/nbio_7_11_0_offset.h"
71 #include "mmhub/mmhub_3_3_0_offset.h"
72 #include "mmhub/mmhub_3_3_0_sh_mask.h"
73
74 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
75 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
76
77 #include "reg_helper.h"
78 #include "dce/dmub_abm.h"
79 #include "dce/dmub_psr.h"
80 #include "dce/dmub_replay.h"
81 #include "dce/dce_aux.h"
82 #include "dce/dce_i2c.h"
83 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
84 #include "vm_helper.h"
85 #include "dcn20/dcn20_vmid.h"
86
87 #include "dml2_0/dml2_wrapper.h"
88
89 #include "link_enc_cfg.h"
90 #define DC_LOGGER_INIT(logger)
91
92 enum dcn351_clk_src_array_id {
93 DCN351_CLK_SRC_PLL0,
94 DCN351_CLK_SRC_PLL1,
95 DCN351_CLK_SRC_PLL2,
96 DCN351_CLK_SRC_PLL3,
97 DCN351_CLK_SRC_PLL4,
98 DCN351_CLK_SRC_TOTAL
99 };
100
101 /* begin *********************
102 * macros to expend register list macro defined in HW object header file
103 */
104
105 /* DCN */
106 /* TODO awful hack. fixup dcn20_dwb.h */
107 #undef BASE_INNER
108 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
109
110 #define BASE(seg) BASE_INNER(seg)
111
112 #define SR(reg_name)\
113 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
114 reg ## reg_name
115
116 #define SR_ARR(reg_name, id) \
117 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
118
119 #define SR_ARR_INIT(reg_name, id, value) \
120 REG_STRUCT[id].reg_name = value
121
122 #define SRI(reg_name, block, id)\
123 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
124 reg ## block ## id ## _ ## reg_name
125
126 #define SRI_ARR(reg_name, block, id)\
127 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
128 reg ## block ## id ## _ ## reg_name
129
130 #define SR_ARR_I2C(reg_name, id) \
131 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
132
133 #define SRI_ARR_I2C(reg_name, block, id)\
134 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 reg ## block ## id ## _ ## reg_name
136
137 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
138 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
139 reg ## block ## id ## _ ## reg_name
140
141 #define SRI2(reg_name, block, id)\
142 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
143 reg ## reg_name
144
145 #define SRI2_ARR(reg_name, block, id)\
146 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
147 reg ## reg_name
148
149 #define SRIR(var_name, reg_name, block, id)\
150 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 reg ## block ## id ## _ ## reg_name
152
153 #define SRII(reg_name, block, id)\
154 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
155 reg ## block ## id ## _ ## reg_name
156
157 #define SRII_ARR_2(reg_name, block, id, inst)\
158 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
159 reg ## block ## id ## _ ## reg_name
160
161 #define SRII_MPC_RMU(reg_name, block, id)\
162 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
163 reg ## block ## id ## _ ## reg_name
164
165 #define SRII_DWB(reg_name, temp_name, block, id)\
166 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
167 reg ## block ## id ## _ ## temp_name
168
169 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
170 .field_name = reg_name ## __ ## field_name ## post_fix
171
172 #define DCCG_SRII(reg_name, block, id)\
173 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
174 reg ## block ## id ## _ ## reg_name
175
176 #define VUPDATE_SRII(reg_name, block, id)\
177 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
178 reg ## reg_name ## _ ## block ## id
179
180 /* NBIO */
181 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
182
183 #define NBIO_BASE(seg) \
184 NBIO_BASE_INNER(seg)
185
186 #define NBIO_SR(reg_name)\
187 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
188 regBIF_BX1_ ## reg_name
189
190 #define NBIO_SR_ARR(reg_name, id)\
191 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
192 regBIF_BX1_ ## reg_name
193
194 #define bios_regs_init() \
195 ( \
196 NBIO_SR(BIOS_SCRATCH_3),\
197 NBIO_SR(BIOS_SCRATCH_6)\
198 )
199
200 static struct bios_registers bios_regs;
201
202 #define clk_src_regs_init(index, pllid)\
203 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
204
205 static struct dce110_clk_src_regs clk_src_regs[5];
206
207 static const struct dce110_clk_src_shift cs_shift = {
208 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
209 };
210
211 static const struct dce110_clk_src_mask cs_mask = {
212 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
213 };
214
215 #define abm_regs_init(id)\
216 ABM_DCN32_REG_LIST_RI(id)
217
218 static struct dce_abm_registers abm_regs[4];
219
220 static const struct dce_abm_shift abm_shift = {
221 ABM_MASK_SH_LIST_DCN35(__SHIFT)
222 };
223
224 static const struct dce_abm_mask abm_mask = {
225 ABM_MASK_SH_LIST_DCN35(_MASK)
226 };
227
228 #define audio_regs_init(id)\
229 AUD_COMMON_REG_LIST_RI(id)
230
231 static struct dce_audio_registers audio_regs[7];
232
233
234 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
235 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
236 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
237 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
238
239 static const struct dce_audio_shift audio_shift = {
240 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
241 };
242
243 static const struct dce_audio_mask audio_mask = {
244 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
245 };
246
247 #define vpg_regs_init(id)\
248 VPG_DCN31_REG_LIST_RI(id)
249
250 static struct dcn31_vpg_registers vpg_regs[10];
251
252 static const struct dcn31_vpg_shift vpg_shift = {
253 DCN31_VPG_MASK_SH_LIST(__SHIFT)
254 };
255
256 static const struct dcn31_vpg_mask vpg_mask = {
257 DCN31_VPG_MASK_SH_LIST(_MASK)
258 };
259
260 #define afmt_regs_init(id)\
261 AFMT_DCN31_REG_LIST_RI(id)
262
263 static struct dcn31_afmt_registers afmt_regs[6];
264
265 static const struct dcn31_afmt_shift afmt_shift = {
266 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
267 };
268
269 static const struct dcn31_afmt_mask afmt_mask = {
270 DCN31_AFMT_MASK_SH_LIST(_MASK)
271 };
272
273 #define apg_regs_init(id)\
274 APG_DCN31_REG_LIST_RI(id)
275
276 static struct dcn31_apg_registers apg_regs[4];
277
278 static const struct dcn31_apg_shift apg_shift = {
279 DCN31_APG_MASK_SH_LIST(__SHIFT)
280 };
281
282 static const struct dcn31_apg_mask apg_mask = {
283 DCN31_APG_MASK_SH_LIST(_MASK)
284 };
285
286 #define stream_enc_regs_init(id)\
287 SE_DCN35_REG_LIST_RI(id)
288
289 static struct dcn10_stream_enc_registers stream_enc_regs[5];
290
291 static const struct dcn10_stream_encoder_shift se_shift = {
292 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
293 };
294
295 static const struct dcn10_stream_encoder_mask se_mask = {
296 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
297 };
298
299 #define aux_regs_init(id)\
300 DCN2_AUX_REG_LIST_RI(id)
301
302 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
303
304 #define hpd_regs_init(id)\
305 HPD_REG_LIST_RI(id)
306
307 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
308
309
310 static const struct dce110_aux_registers_shift aux_shift = {
311 DCN_AUX_MASK_SH_LIST(__SHIFT)
312 };
313
314 static const struct dce110_aux_registers_mask aux_mask = {
315 DCN_AUX_MASK_SH_LIST(_MASK)
316 };
317
318 #define link_regs_init(id, phyid)\
319 ( \
320 LE_DCN35_REG_LIST_RI(id), \
321 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
322 )
323
324 static struct dcn10_link_enc_registers link_enc_regs[5];
325
326 static const struct dcn10_link_enc_shift le_shift = {
327 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
328 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
329 };
330
331 static const struct dcn10_link_enc_mask le_mask = {
332 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
333 //DPCS_DCN31_MASK_SH_LIST(_MASK)
334 };
335
336 #define hpo_dp_stream_encoder_reg_init(id)\
337 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
338
339 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
340
341 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
342 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
343 };
344
345 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
346 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
347 };
348
349 #define hpo_dp_link_encoder_reg_init(id)\
350 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
351 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
352 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
353 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
354 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
355
356 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
357
358 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
359 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
360 };
361
362 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
363 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
364 };
365
366 #define dpp_regs_init(id)\
367 DPP_REG_LIST_DCN35_RI(id)
368
369 static struct dcn3_dpp_registers dpp_regs[4];
370
371 static const struct dcn35_dpp_shift tf_shift = {
372 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
373 };
374
375 static const struct dcn35_dpp_mask tf_mask = {
376 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
377 };
378
379 #define opp_regs_init(id)\
380 OPP_REG_LIST_DCN35_RI(id)
381
382 static struct dcn35_opp_registers opp_regs[4];
383
384 static const struct dcn35_opp_shift opp_shift = {
385 OPP_MASK_SH_LIST_DCN35(__SHIFT)
386 };
387
388 static const struct dcn35_opp_mask opp_mask = {
389 OPP_MASK_SH_LIST_DCN35(_MASK)
390 };
391
392 #define aux_engine_regs_init(id)\
393 ( \
394 AUX_COMMON_REG_LIST0_RI(id), \
395 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
396 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
397 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
398 )
399
400 static struct dce110_aux_registers aux_engine_regs[5];
401
402 #define dwbc_regs_dcn3_init(id)\
403 DWBC_COMMON_REG_LIST_DCN30_RI(id)
404
405 static struct dcn30_dwbc_registers dwbc35_regs[1];
406
407 static const struct dcn35_dwbc_shift dwbc35_shift = {
408 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
409 };
410
411 static const struct dcn35_dwbc_mask dwbc35_mask = {
412 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
413 };
414
415 #define mcif_wb_regs_dcn3_init(id)\
416 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
417
418 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
419
420 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
421 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
422 };
423
424 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
425 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
426 };
427
428 #define dsc_regsDCN35_init(id)\
429 DSC_REG_LIST_DCN20_RI(id)
430
431 static struct dcn20_dsc_registers dsc_regs[4];
432
433 static const struct dcn35_dsc_shift dsc_shift = {
434 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
435 };
436
437 static const struct dcn35_dsc_mask dsc_mask = {
438 DSC_REG_LIST_SH_MASK_DCN35(_MASK)
439 };
440
441 static struct dcn30_mpc_registers mpc_regs;
442
443 #define dcn_mpc_regs_init() \
444 MPC_REG_LIST_DCN3_2_RI(0),\
445 MPC_REG_LIST_DCN3_2_RI(1),\
446 MPC_REG_LIST_DCN3_2_RI(2),\
447 MPC_REG_LIST_DCN3_2_RI(3),\
448 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
449 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
450 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
451 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
452 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
453
454 static const struct dcn30_mpc_shift mpc_shift = {
455 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
456 };
457
458 static const struct dcn30_mpc_mask mpc_mask = {
459 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
460 };
461
462 #define optc_regs_init(id)\
463 OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
464
465 static struct dcn_optc_registers optc_regs[4];
466
467 static const struct dcn_optc_shift optc_shift = {
468 OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
469 };
470
471 static const struct dcn_optc_mask optc_mask = {
472 OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
473 };
474
475 #define hubp_regs_init(id)\
476 HUBP_REG_LIST_DCN30_RI(id)
477
478 static struct dcn_hubp2_registers hubp_regs[4];
479
480
481 static const struct dcn35_hubp2_shift hubp_shift = {
482 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
483 };
484
485 static const struct dcn35_hubp2_mask hubp_mask = {
486 HUBP_MASK_SH_LIST_DCN35(_MASK)
487 };
488
489 static struct dcn_hubbub_registers hubbub_reg;
490
491 #define hubbub_reg_init()\
492 HUBBUB_REG_LIST_DCN35(0)
493
494 static const struct dcn_hubbub_shift hubbub_shift = {
495 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
496 };
497
498 static const struct dcn_hubbub_mask hubbub_mask = {
499 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
500 };
501
502 static struct dccg_registers dccg_regs;
503
504 #define dccg_regs_init()\
505 DCCG_REG_LIST_DCN35()
506
507 static const struct dccg_shift dccg_shift = {
508 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
509 };
510
511 static const struct dccg_mask dccg_mask = {
512 DCCG_MASK_SH_LIST_DCN35(_MASK)
513 };
514
515 static struct pg_cntl_registers pg_cntl_regs;
516
517 #define pg_cntl_dcn35_regs_init() \
518 PG_CNTL_REG_LIST_DCN35()
519
520 static const struct pg_cntl_shift pg_cntl_shift = {
521 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
522 };
523
524 static const struct pg_cntl_mask pg_cntl_mask = {
525 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
526 };
527
528 #define SRII2(reg_name_pre, reg_name_post, id)\
529 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
530 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
531 reg ## reg_name_pre ## id ## _ ## reg_name_post
532
533 static struct dce_hwseq_registers hwseq_reg;
534
535 #define hwseq_reg_init()\
536 HWSEQ_DCN35_REG_LIST()
537
538 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
539 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
540 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
541 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
542 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
543 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
544 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
545 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
546 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
547 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
548 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
549 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
550 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
551 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
552 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
553 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
554 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
555 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
556 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
557 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
558 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
559 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
560 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
561 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
562 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
563 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
564 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
565 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
566 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
567 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
568 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
569 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
570 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
571 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
572 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
573 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
574 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
575 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
576 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
577 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
578 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
579 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
580 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
581 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
582 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
583 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
584 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
585 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
586 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
587 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
588 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
589 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
590 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
591 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
592 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
593 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
594 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
595 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
596 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
597 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
598 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
599 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
600 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
601 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
602 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
603 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
604 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
605 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
606 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
607 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
608 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
609 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
610 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
611 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
612 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
613 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
614 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
615 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
616 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
617 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
618 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
619 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
620 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
621 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
622 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
623 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
624 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
625 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
626
627 static const struct dce_hwseq_shift hwseq_shift = {
628 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
629 };
630
631 static const struct dce_hwseq_mask hwseq_mask = {
632 HWSEQ_DCN35_MASK_SH_LIST(_MASK)
633 };
634
635 #define vmid_regs_init(id)\
636 DCN20_VMID_REG_LIST_RI(id)
637
638 static struct dcn_vmid_registers vmid_regs[16];
639
640 static const struct dcn20_vmid_shift vmid_shifts = {
641 DCN20_VMID_MASK_SH_LIST(__SHIFT)
642 };
643
644 static const struct dcn20_vmid_mask vmid_masks = {
645 DCN20_VMID_MASK_SH_LIST(_MASK)
646 };
647
648 static struct dcn_dio_registers dio_regs;
649
650 #define DIO_MASK_SH_LIST(mask_sh)\
651 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
652
653 static const struct dcn_dio_shift dio_shift = {
654 DIO_MASK_SH_LIST(__SHIFT)
655 };
656
657 static const struct dcn_dio_mask dio_mask = {
658 DIO_MASK_SH_LIST(_MASK)
659 };
660
661 static const struct resource_caps res_cap_dcn351 = {
662 .num_timing_generator = 4,
663 .num_opp = 4,
664 .num_video_plane = 4,
665 .num_audio = 5,
666 .num_stream_encoder = 5,
667 .num_dig_link_enc = 5,
668 .num_hpo_dp_stream_encoder = 4,
669 .num_hpo_dp_link_encoder = 2,
670 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
671 .num_dwb = 1,
672 .num_ddc = 5,
673 .num_vmid = 16,
674 .num_mpc_3dlut = 2,
675 .num_dsc = 4,
676 };
677
678 static const struct dc_plane_cap plane_cap = {
679 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
680 .per_pixel_alpha = true,
681
682 .pixel_format_support = {
683 .argb8888 = true,
684 .nv12 = true,
685 .fp16 = true,
686 .p010 = true,
687 .ayuv = false,
688 },
689
690 .max_upscale_factor = {
691 .argb8888 = 16000,
692 .nv12 = 16000,
693 .fp16 = 16000
694 },
695
696 // 6:1 downscaling ratio: 1000/6 = 166.666
697 .max_downscale_factor = {
698 .argb8888 = 250,
699 .nv12 = 167,
700 .fp16 = 167
701 },
702 64,
703 64
704 };
705
706 static const struct dc_debug_options debug_defaults_drv = {
707 .disable_dmcu = true,
708 .force_abm_enable = false,
709 .clock_trace = true,
710 .disable_pplib_clock_request = false,
711 .pipe_split_policy = MPC_SPLIT_AVOID,
712 .force_single_disp_pipe_split = false,
713 .disable_dcc = DCC_ENABLE,
714 .disable_dpp_power_gate = true,
715 .disable_hubp_power_gate = true,
716 .disable_optc_power_gate = true, /*should the same as above two*/
717 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
718 .disable_clock_gate = false,
719 .disable_dsc_power_gate = true,
720 .vsr_support = true,
721 .performance_trace = false,
722 .max_downscale_src_width = 4096,/*upto true 4k*/
723 .disable_pplib_wm_range = false,
724 .scl_reset_length10 = true,
725 .sanity_checks = false,
726 .underflow_assert_delay_us = 0xFFFFFFFF,
727 .dwb_fi_phase = -1, // -1 = disable,
728 .dmub_command_table = true,
729 .pstate_enabled = true,
730 .use_max_lb = true,
731 .enable_mem_low_power = {
732 .bits = {
733 .vga = false,
734 .i2c = true,
735 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
736 .dscl = true,
737 .cm = true,
738 .mpc = true,
739 .optc = true,
740 .vpg = true,
741 .afmt = true,
742 }
743 },
744 .root_clock_optimization = {
745 .bits = {
746 .dpp = true,
747 .dsc = true,/*dscclk and dsc pg*/
748 .hdmistream = true,
749 .hdmichar = true,
750 .dpstream = true,
751 .symclk32_se = true,
752 .symclk32_le = false,
753 .symclk_fe = true,
754 .physymclk = false,
755 .dpiasymclk = true,
756 }
757 },
758 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
759 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
760 .minimum_z8_residency_time = 1,
761 .using_dml2 = true,
762 .support_eDP1_5 = true,
763 .enable_hpo_pg_support = false,
764 .enable_single_display_2to1_odm_policy = true,
765 .disable_idle_power_optimizations = false,
766 .dmcub_emulation = false,
767 .disable_boot_optimizations = false,
768 .disable_unbounded_requesting = false,
769 .disable_mem_low_power = false,
770 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
771 .enable_double_buffered_dsc_pg_support = true,
772 .enable_dp_dig_pixel_rate_div_policy = 1,
773 .disable_z10 = false,
774 .ignore_pg = true,
775 .psp_disabled_wa = true,
776 .ips2_eval_delay_us = 2000,
777 .ips2_entry_delay_us = 800,
778 .disable_dmub_reallow_idle = false,
779 .static_screen_wait_frames = 2,
780 .notify_dpia_hr_bw = true,
781 .min_disp_clk_khz = 50000,
782 };
783
784 static const struct dc_check_config config_defaults = {
785 .enable_legacy_fast_update = false,
786 };
787
788 static const struct dc_panel_config panel_config_defaults = {
789 .psr = {
790 .disable_psr = false,
791 .disallow_psrsu = false,
792 .disallow_replay = false,
793 },
794 .ilr = {
795 .optimize_edp_link_rate = true,
796 },
797 };
798
dcn35_dpp_destroy(struct dpp ** dpp)799 static void dcn35_dpp_destroy(struct dpp **dpp)
800 {
801 kfree(TO_DCN20_DPP(*dpp));
802 *dpp = NULL;
803 }
804
dcn35_dpp_create(struct dc_context * ctx,uint32_t inst)805 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
806 {
807 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);
808 bool success = (dpp != NULL);
809
810 if (!success)
811 return NULL;
812
813 #undef REG_STRUCT
814 #define REG_STRUCT dpp_regs
815 dpp_regs_init(0),
816 dpp_regs_init(1),
817 dpp_regs_init(2),
818 dpp_regs_init(3);
819
820 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
821 &tf_mask);
822 if (success) {
823 dpp35_set_fgcg(
824 dpp,
825 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
826 return &dpp->base;
827 }
828
829 BREAK_TO_DEBUGGER();
830 kfree(dpp);
831 return NULL;
832 }
833
dcn35_opp_create(struct dc_context * ctx,uint32_t inst)834 static struct output_pixel_processor *dcn35_opp_create(
835 struct dc_context *ctx, uint32_t inst)
836 {
837 struct dcn20_opp *opp =
838 kzalloc_obj(struct dcn20_opp);
839
840 if (!opp) {
841 BREAK_TO_DEBUGGER();
842 return NULL;
843 }
844
845 #undef REG_STRUCT
846 #define REG_STRUCT opp_regs
847 opp_regs_init(0),
848 opp_regs_init(1),
849 opp_regs_init(2),
850 opp_regs_init(3);
851
852 dcn35_opp_construct(opp, ctx, inst,
853 &opp_regs[inst], &opp_shift, &opp_mask);
854
855 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
856
857 return &opp->base;
858 }
859
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)860 static struct dce_aux *dcn31_aux_engine_create(
861 struct dc_context *ctx,
862 uint32_t inst)
863 {
864 struct aux_engine_dce110 *aux_engine =
865 kzalloc_obj(struct aux_engine_dce110);
866
867 if (!aux_engine)
868 return NULL;
869
870 #undef REG_STRUCT
871 #define REG_STRUCT aux_engine_regs
872 aux_engine_regs_init(0),
873 aux_engine_regs_init(1),
874 aux_engine_regs_init(2),
875 aux_engine_regs_init(3),
876 aux_engine_regs_init(4);
877
878 dce110_aux_engine_construct(aux_engine, ctx, inst,
879 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
880 &aux_engine_regs[inst],
881 &aux_mask,
882 &aux_shift,
883 ctx->dc->caps.extended_aux_timeout_support);
884
885 return &aux_engine->base;
886 }
887
888 #define i2c_inst_regs_init(id)\
889 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
890
891 static struct dce_i2c_registers i2c_hw_regs[5];
892
893 static const struct dce_i2c_shift i2c_shifts = {
894 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
895 };
896
897 static const struct dce_i2c_mask i2c_masks = {
898 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
899 };
900
901 /* ========================================================== */
902
903 /*
904 * DPIA index | Preferred Encoder | Host Router
905 * 0 | C | 0
906 * 1 | First Available | 0
907 * 2 | D | 1
908 * 3 | First Available | 1
909 */
910 /* ========================================================== */
911 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
912 ENGINE_ID_DIGC,
913 ENGINE_ID_DIGC,
914 ENGINE_ID_DIGD,
915 ENGINE_ID_DIGD
916 };
917
dcn351_get_preferred_eng_id_dpia(unsigned int dpia_index)918 static enum engine_id dcn351_get_preferred_eng_id_dpia(unsigned int dpia_index)
919 {
920 return dpia_to_preferred_enc_id_table[dpia_index];
921 }
922
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)923 static struct dce_i2c_hw *dcn31_i2c_hw_create(
924 struct dc_context *ctx,
925 uint32_t inst)
926 {
927 struct dce_i2c_hw *dce_i2c_hw =
928 kzalloc_obj(struct dce_i2c_hw);
929
930 if (!dce_i2c_hw)
931 return NULL;
932
933 #undef REG_STRUCT
934 #define REG_STRUCT i2c_hw_regs
935 i2c_inst_regs_init(1),
936 i2c_inst_regs_init(2),
937 i2c_inst_regs_init(3),
938 i2c_inst_regs_init(4),
939 i2c_inst_regs_init(5);
940
941 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
942 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
943
944 return dce_i2c_hw;
945 }
dcn35_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)946 static struct mpc *dcn35_mpc_create(
947 struct dc_context *ctx,
948 int num_mpcc,
949 int num_rmu)
950 {
951 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
952
953 if (!mpc30)
954 return NULL;
955
956 #undef REG_STRUCT
957 #define REG_STRUCT mpc_regs
958 dcn_mpc_regs_init();
959
960 dcn32_mpc_construct(mpc30, ctx,
961 &mpc_regs,
962 &mpc_shift,
963 &mpc_mask,
964 num_mpcc,
965 num_rmu);
966
967 return &mpc30->base;
968 }
969
dcn351_dio_create(struct dc_context * ctx)970 static struct dio *dcn351_dio_create(struct dc_context *ctx)
971 {
972 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
973
974 if (!dio10)
975 return NULL;
976
977 #undef REG_STRUCT
978 #define REG_STRUCT dio_regs
979 DIO_REG_LIST_DCN10();
980
981 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
982
983 return &dio10->base;
984 }
985
dcn35_hubbub_create(struct dc_context * ctx)986 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
987 {
988 int i;
989
990 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
991
992 if (!hubbub3)
993 return NULL;
994
995 #undef REG_STRUCT
996 #define REG_STRUCT hubbub_reg
997 hubbub_reg_init();
998
999 #undef REG_STRUCT
1000 #define REG_STRUCT vmid_regs
1001 vmid_regs_init(0),
1002 vmid_regs_init(1),
1003 vmid_regs_init(2),
1004 vmid_regs_init(3),
1005 vmid_regs_init(4),
1006 vmid_regs_init(5),
1007 vmid_regs_init(6),
1008 vmid_regs_init(7),
1009 vmid_regs_init(8),
1010 vmid_regs_init(9),
1011 vmid_regs_init(10),
1012 vmid_regs_init(11),
1013 vmid_regs_init(12),
1014 vmid_regs_init(13),
1015 vmid_regs_init(14),
1016 vmid_regs_init(15);
1017
1018 hubbub35_construct(hubbub3, ctx,
1019 &hubbub_reg,
1020 &hubbub_shift,
1021 &hubbub_mask,
1022 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
1023 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
1024 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1025
1026
1027 for (i = 0; i < res_cap_dcn351.num_vmid; i++) {
1028 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1029
1030 vmid->ctx = ctx;
1031
1032 vmid->regs = &vmid_regs[i];
1033 vmid->shifts = &vmid_shifts;
1034 vmid->masks = &vmid_masks;
1035 }
1036
1037 return &hubbub3->base;
1038 }
1039
dcn35_timing_generator_create(struct dc_context * ctx,uint32_t instance)1040 static struct timing_generator *dcn35_timing_generator_create(
1041 struct dc_context *ctx,
1042 uint32_t instance)
1043 {
1044 struct optc *tgn10 =
1045 kzalloc_obj(struct optc);
1046
1047 if (!tgn10)
1048 return NULL;
1049
1050 #undef REG_STRUCT
1051 #define REG_STRUCT optc_regs
1052 optc_regs_init(0),
1053 optc_regs_init(1),
1054 optc_regs_init(2),
1055 optc_regs_init(3);
1056
1057 tgn10->base.inst = instance;
1058 tgn10->base.ctx = ctx;
1059
1060 tgn10->tg_regs = &optc_regs[instance];
1061 tgn10->tg_shift = &optc_shift;
1062 tgn10->tg_mask = &optc_mask;
1063
1064 dcn35_timing_generator_init(tgn10);
1065
1066 return &tgn10->base;
1067 }
1068
1069 static const struct encoder_feature_support link_enc_feature = {
1070 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1071 .max_hdmi_pixel_clock = 600000,
1072 .hdmi_ycbcr420_supported = true,
1073 .dp_ycbcr420_supported = true,
1074 .fec_supported = true,
1075 .flags.bits.IS_HBR2_CAPABLE = true,
1076 .flags.bits.IS_HBR3_CAPABLE = true,
1077 .flags.bits.IS_TPS3_CAPABLE = true,
1078 .flags.bits.IS_TPS4_CAPABLE = true
1079 };
1080
dcn35_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1081 static struct link_encoder *dcn35_link_encoder_create(
1082 struct dc_context *ctx,
1083 const struct encoder_init_data *enc_init_data)
1084 {
1085 struct dcn20_link_encoder *enc20 =
1086 kzalloc_obj(struct dcn20_link_encoder);
1087
1088 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1089 return NULL;
1090
1091 #undef REG_STRUCT
1092 #define REG_STRUCT link_enc_aux_regs
1093 aux_regs_init(0),
1094 aux_regs_init(1),
1095 aux_regs_init(2),
1096 aux_regs_init(3),
1097 aux_regs_init(4);
1098
1099 #undef REG_STRUCT
1100 #define REG_STRUCT link_enc_hpd_regs
1101 hpd_regs_init(0),
1102 hpd_regs_init(1),
1103 hpd_regs_init(2),
1104 hpd_regs_init(3),
1105 hpd_regs_init(4);
1106
1107 #undef REG_STRUCT
1108 #define REG_STRUCT link_enc_regs
1109 link_regs_init(0, A),
1110 link_regs_init(1, B),
1111 link_regs_init(2, C),
1112 link_regs_init(3, D),
1113 link_regs_init(4, E);
1114
1115 dcn35_link_encoder_construct(enc20,
1116 enc_init_data,
1117 &link_enc_feature,
1118 &link_enc_regs[enc_init_data->transmitter],
1119 &link_enc_aux_regs[enc_init_data->channel - 1],
1120 &link_enc_hpd_regs[enc_init_data->hpd_source],
1121 &le_shift,
1122 &le_mask);
1123
1124 return &enc20->enc10.base;
1125 }
1126
1127 /* Create a minimal link encoder object not associated with a particular
1128 * physical connector.
1129 * resource_funcs.link_enc_create_minimal
1130 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1131 static struct link_encoder *dcn31_link_enc_create_minimal(
1132 struct dc_context *ctx, enum engine_id eng_id)
1133 {
1134 struct dcn20_link_encoder *enc20;
1135
1136 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1137 return NULL;
1138
1139 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1140 if (!enc20)
1141 return NULL;
1142
1143 dcn31_link_encoder_construct_minimal(
1144 enc20,
1145 ctx,
1146 &link_enc_feature,
1147 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1148 eng_id);
1149
1150 return &enc20->enc10.base;
1151 }
1152
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1153 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1154 {
1155 struct dcn31_panel_cntl *panel_cntl =
1156 kzalloc_obj(struct dcn31_panel_cntl);
1157
1158 if (!panel_cntl)
1159 return NULL;
1160
1161 dcn31_panel_cntl_construct(panel_cntl, init_data);
1162
1163 return &panel_cntl->base;
1164 }
1165
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1166 static void read_dce_straps(
1167 struct dc_context *ctx,
1168 struct resource_straps *straps)
1169 {
1170 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1171 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1172
1173 }
1174
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1175 static struct audio *dcn31_create_audio(
1176 struct dc_context *ctx, unsigned int inst)
1177 {
1178
1179 #undef REG_STRUCT
1180 #define REG_STRUCT audio_regs
1181 audio_regs_init(0),
1182 audio_regs_init(1),
1183 audio_regs_init(2),
1184 audio_regs_init(3),
1185 audio_regs_init(4);
1186 audio_regs_init(5);
1187 audio_regs_init(6);
1188
1189 return dce_audio_create(ctx, inst,
1190 &audio_regs[inst], &audio_shift, &audio_mask);
1191 }
1192
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1193 static struct vpg *dcn31_vpg_create(
1194 struct dc_context *ctx,
1195 uint32_t inst)
1196 {
1197 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1198
1199 if (!vpg31)
1200 return NULL;
1201
1202 #undef REG_STRUCT
1203 #define REG_STRUCT vpg_regs
1204 vpg_regs_init(0),
1205 vpg_regs_init(1),
1206 vpg_regs_init(2),
1207 vpg_regs_init(3),
1208 vpg_regs_init(4),
1209 vpg_regs_init(5),
1210 vpg_regs_init(6),
1211 vpg_regs_init(7),
1212 vpg_regs_init(8),
1213 vpg_regs_init(9);
1214
1215 vpg31_construct(vpg31, ctx, inst,
1216 &vpg_regs[inst],
1217 &vpg_shift,
1218 &vpg_mask);
1219
1220 return &vpg31->base;
1221 }
1222
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1223 static struct afmt *dcn31_afmt_create(
1224 struct dc_context *ctx,
1225 uint32_t inst)
1226 {
1227 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1228
1229 if (!afmt31)
1230 return NULL;
1231
1232 #undef REG_STRUCT
1233 #define REG_STRUCT afmt_regs
1234 afmt_regs_init(0),
1235 afmt_regs_init(1),
1236 afmt_regs_init(2),
1237 afmt_regs_init(3),
1238 afmt_regs_init(4),
1239 afmt_regs_init(5);
1240
1241 afmt31_construct(afmt31, ctx, inst,
1242 &afmt_regs[inst],
1243 &afmt_shift,
1244 &afmt_mask);
1245
1246 // Light sleep by default, no need to power down here
1247
1248 return &afmt31->base;
1249 }
1250
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1251 static struct apg *dcn31_apg_create(
1252 struct dc_context *ctx,
1253 uint32_t inst)
1254 {
1255 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1256
1257 if (!apg31)
1258 return NULL;
1259
1260 #undef REG_STRUCT
1261 #define REG_STRUCT apg_regs
1262 apg_regs_init(0),
1263 apg_regs_init(1),
1264 apg_regs_init(2),
1265 apg_regs_init(3);
1266
1267 apg31_construct(apg31, ctx, inst,
1268 &apg_regs[inst],
1269 &apg_shift,
1270 &apg_mask);
1271
1272 return &apg31->base;
1273 }
1274
dcn35_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1275 static struct stream_encoder *dcn35_stream_encoder_create(
1276 enum engine_id eng_id,
1277 struct dc_context *ctx)
1278 {
1279 struct dcn10_stream_encoder *enc1;
1280 struct vpg *vpg;
1281 struct afmt *afmt;
1282 int vpg_inst;
1283 int afmt_inst;
1284
1285 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1286 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1287 return NULL;
1288
1289 vpg_inst = eng_id;
1290 afmt_inst = eng_id;
1291
1292 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1293 vpg = dcn31_vpg_create(ctx, vpg_inst);
1294 afmt = dcn31_afmt_create(ctx, afmt_inst);
1295
1296 if (!enc1 || !vpg || !afmt) {
1297 kfree(enc1);
1298 kfree(vpg);
1299 kfree(afmt);
1300 return NULL;
1301 }
1302
1303 #undef REG_STRUCT
1304 #define REG_STRUCT stream_enc_regs
1305 stream_enc_regs_init(0),
1306 stream_enc_regs_init(1),
1307 stream_enc_regs_init(2),
1308 stream_enc_regs_init(3),
1309 stream_enc_regs_init(4);
1310
1311 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1312 eng_id, vpg, afmt,
1313 &stream_enc_regs[eng_id],
1314 &se_shift, &se_mask);
1315
1316 return &enc1->base;
1317 }
1318
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1319 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1320 enum engine_id eng_id,
1321 struct dc_context *ctx)
1322 {
1323 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1324 struct vpg *vpg;
1325 struct apg *apg;
1326 uint32_t hpo_dp_inst;
1327 uint32_t vpg_inst;
1328 uint32_t apg_inst;
1329
1330 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1331 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1332
1333 /* Mapping of VPG register blocks to HPO DP block instance:
1334 * VPG[6] -> HPO_DP[0]
1335 * VPG[7] -> HPO_DP[1]
1336 * VPG[8] -> HPO_DP[2]
1337 * VPG[9] -> HPO_DP[3]
1338 */
1339 vpg_inst = hpo_dp_inst + 6;
1340
1341 /* Mapping of APG register blocks to HPO DP block instance:
1342 * APG[0] -> HPO_DP[0]
1343 * APG[1] -> HPO_DP[1]
1344 * APG[2] -> HPO_DP[2]
1345 * APG[3] -> HPO_DP[3]
1346 */
1347 apg_inst = hpo_dp_inst;
1348
1349 /* allocate HPO stream encoder and create VPG sub-block */
1350 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1351 vpg = dcn31_vpg_create(ctx, vpg_inst);
1352 apg = dcn31_apg_create(ctx, apg_inst);
1353
1354 if (!hpo_dp_enc31 || !vpg || !apg) {
1355 kfree(hpo_dp_enc31);
1356 kfree(vpg);
1357 kfree(apg);
1358 return NULL;
1359 }
1360
1361 #undef REG_STRUCT
1362 #define REG_STRUCT hpo_dp_stream_enc_regs
1363 hpo_dp_stream_encoder_reg_init(0),
1364 hpo_dp_stream_encoder_reg_init(1),
1365 hpo_dp_stream_encoder_reg_init(2),
1366 hpo_dp_stream_encoder_reg_init(3);
1367
1368 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1369 hpo_dp_inst, eng_id, vpg, apg,
1370 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1371 &hpo_dp_se_shift, &hpo_dp_se_mask);
1372
1373 return &hpo_dp_enc31->base;
1374 }
1375
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1376 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1377 uint8_t inst,
1378 struct dc_context *ctx)
1379 {
1380 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1381
1382 /* allocate HPO link encoder */
1383 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1384 if (!hpo_dp_enc31)
1385 return NULL; /* out of memory */
1386
1387 #undef REG_STRUCT
1388 #define REG_STRUCT hpo_dp_link_enc_regs
1389 hpo_dp_link_encoder_reg_init(0),
1390 hpo_dp_link_encoder_reg_init(1);
1391
1392 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1393 &hpo_dp_link_enc_regs[inst],
1394 &hpo_dp_le_shift, &hpo_dp_le_mask);
1395
1396 return &hpo_dp_enc31->base;
1397 }
1398
dcn351_hwseq_create(struct dc_context * ctx)1399 static struct dce_hwseq *dcn351_hwseq_create(
1400 struct dc_context *ctx)
1401 {
1402 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1403
1404 #undef REG_STRUCT
1405 #define REG_STRUCT hwseq_reg
1406 hwseq_reg_init();
1407
1408 if (hws) {
1409 hws->ctx = ctx;
1410 hws->regs = &hwseq_reg;
1411 hws->shifts = &hwseq_shift;
1412 hws->masks = &hwseq_mask;
1413 }
1414 return hws;
1415 }
1416 static const struct resource_create_funcs res_create_funcs = {
1417 .read_dce_straps = read_dce_straps,
1418 .create_audio = dcn31_create_audio,
1419 .create_stream_encoder = dcn35_stream_encoder_create,
1420 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1421 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1422 .create_hwseq = dcn351_hwseq_create,
1423 };
1424
dcn351_resource_destruct(struct dcn351_resource_pool * pool)1425 static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
1426 {
1427 unsigned int i;
1428
1429 for (i = 0; i < pool->base.stream_enc_count; i++) {
1430 if (pool->base.stream_enc[i] != NULL) {
1431 if (pool->base.stream_enc[i]->vpg != NULL) {
1432 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1433 pool->base.stream_enc[i]->vpg = NULL;
1434 }
1435 if (pool->base.stream_enc[i]->afmt != NULL) {
1436 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1437 pool->base.stream_enc[i]->afmt = NULL;
1438 }
1439 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1440 pool->base.stream_enc[i] = NULL;
1441 }
1442 }
1443
1444 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1445 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1446 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1447 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1448 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1449 }
1450 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1451 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1452 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1453 }
1454 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1455 pool->base.hpo_dp_stream_enc[i] = NULL;
1456 }
1457 }
1458
1459 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1460 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1461 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1462 pool->base.hpo_dp_link_enc[i] = NULL;
1463 }
1464 }
1465
1466 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1467 if (pool->base.dscs[i] != NULL)
1468 dcn20_dsc_destroy(&pool->base.dscs[i]);
1469 }
1470
1471 if (pool->base.mpc != NULL) {
1472 kfree(TO_DCN20_MPC(pool->base.mpc));
1473 pool->base.mpc = NULL;
1474 }
1475 if (pool->base.hubbub != NULL) {
1476 kfree(pool->base.hubbub);
1477 pool->base.hubbub = NULL;
1478 }
1479 for (i = 0; i < pool->base.pipe_count; i++) {
1480 if (pool->base.dpps[i] != NULL)
1481 dcn35_dpp_destroy(&pool->base.dpps[i]);
1482
1483 if (pool->base.ipps[i] != NULL)
1484 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1485
1486 if (pool->base.hubps[i] != NULL) {
1487 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1488 pool->base.hubps[i] = NULL;
1489 }
1490
1491 if (pool->base.irqs != NULL) {
1492 dal_irq_service_destroy(&pool->base.irqs);
1493 }
1494 }
1495
1496 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1497 if (pool->base.engines[i] != NULL)
1498 dce110_engine_destroy(&pool->base.engines[i]);
1499 if (pool->base.hw_i2cs[i] != NULL) {
1500 kfree(pool->base.hw_i2cs[i]);
1501 pool->base.hw_i2cs[i] = NULL;
1502 }
1503 if (pool->base.sw_i2cs[i] != NULL) {
1504 kfree(pool->base.sw_i2cs[i]);
1505 pool->base.sw_i2cs[i] = NULL;
1506 }
1507 }
1508
1509 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1510 if (pool->base.opps[i] != NULL)
1511 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1512 }
1513
1514 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1515 if (pool->base.timing_generators[i] != NULL) {
1516 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1517 pool->base.timing_generators[i] = NULL;
1518 }
1519 }
1520
1521 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1522 if (pool->base.dwbc[i] != NULL) {
1523 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1524 pool->base.dwbc[i] = NULL;
1525 }
1526 if (pool->base.mcif_wb[i] != NULL) {
1527 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1528 pool->base.mcif_wb[i] = NULL;
1529 }
1530 }
1531
1532 for (i = 0; i < pool->base.audio_count; i++) {
1533 if (pool->base.audios[i])
1534 dce_aud_destroy(&pool->base.audios[i]);
1535 }
1536
1537 for (i = 0; i < pool->base.clk_src_count; i++) {
1538 if (pool->base.clock_sources[i] != NULL) {
1539 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1540 pool->base.clock_sources[i] = NULL;
1541 }
1542 }
1543
1544 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1545 if (pool->base.mpc_lut[i] != NULL) {
1546 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1547 pool->base.mpc_lut[i] = NULL;
1548 }
1549 if (pool->base.mpc_shaper[i] != NULL) {
1550 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1551 pool->base.mpc_shaper[i] = NULL;
1552 }
1553 }
1554
1555 if (pool->base.dp_clock_source != NULL) {
1556 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1557 pool->base.dp_clock_source = NULL;
1558 }
1559
1560 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1561 if (pool->base.multiple_abms[i] != NULL)
1562 dce_abm_destroy(&pool->base.multiple_abms[i]);
1563 }
1564
1565 if (pool->base.psr != NULL)
1566 dmub_psr_destroy(&pool->base.psr);
1567
1568 if (pool->base.replay != NULL)
1569 dmub_replay_destroy(&pool->base.replay);
1570
1571 if (pool->base.pg_cntl != NULL)
1572 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1573
1574 if (pool->base.dccg != NULL)
1575 dcn_dccg_destroy(&pool->base.dccg);
1576
1577 if (pool->base.dio != NULL) {
1578 kfree(TO_DCN10_DIO(pool->base.dio));
1579 pool->base.dio = NULL;
1580 }
1581 }
1582
dcn35_hubp_create(struct dc_context * ctx,uint32_t inst)1583 static struct hubp *dcn35_hubp_create(
1584 struct dc_context *ctx,
1585 uint32_t inst)
1586 {
1587 struct dcn20_hubp *hubp2 =
1588 kzalloc_obj(struct dcn20_hubp);
1589
1590 if (!hubp2)
1591 return NULL;
1592
1593 #undef REG_STRUCT
1594 #define REG_STRUCT hubp_regs
1595 hubp_regs_init(0),
1596 hubp_regs_init(1),
1597 hubp_regs_init(2),
1598 hubp_regs_init(3);
1599
1600 if (hubp35_construct(hubp2, ctx, inst,
1601 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1602 return &hubp2->base;
1603
1604 BREAK_TO_DEBUGGER();
1605 kfree(hubp2);
1606 return NULL;
1607 }
1608
dcn35_dwbc_init(struct dcn30_dwbc * dwbc30,struct dc_context * ctx)1609 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1610 {
1611 dcn35_dwbc_set_fgcg(
1612 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1613 }
1614
dcn35_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1615 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1616 {
1617 int i;
1618 uint32_t pipe_count = pool->res_cap->num_dwb;
1619
1620 for (i = 0; i < pipe_count; i++) {
1621 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1622
1623 if (!dwbc30) {
1624 dm_error("DC: failed to create dwbc30!\n");
1625 return false;
1626 }
1627
1628 #undef REG_STRUCT
1629 #define REG_STRUCT dwbc35_regs
1630 dwbc_regs_dcn3_init(0);
1631
1632 dcn35_dwbc_construct(dwbc30, ctx,
1633 &dwbc35_regs[i],
1634 &dwbc35_shift,
1635 &dwbc35_mask,
1636 i);
1637
1638 pool->dwbc[i] = &dwbc30->base;
1639
1640 dcn35_dwbc_init(dwbc30, ctx);
1641 }
1642 return true;
1643 }
1644
dcn35_mmhubbub_init(struct dcn30_mmhubbub * mcif_wb30,struct dc_context * ctx)1645 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1646 struct dc_context *ctx)
1647 {
1648 dcn35_mmhubbub_set_fgcg(
1649 mcif_wb30,
1650 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1651 }
1652
dcn35_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1653 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1654 {
1655 int i;
1656 uint32_t pipe_count = pool->res_cap->num_dwb;
1657
1658 for (i = 0; i < pipe_count; i++) {
1659 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1660
1661 if (!mcif_wb30) {
1662 dm_error("DC: failed to create mcif_wb30!\n");
1663 return false;
1664 }
1665
1666 #undef REG_STRUCT
1667 #define REG_STRUCT mcif_wb35_regs
1668 mcif_wb_regs_dcn3_init(0);
1669
1670 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1671 &mcif_wb35_regs[i],
1672 &mcif_wb35_shift,
1673 &mcif_wb35_mask,
1674 i);
1675
1676 dcn35_mmhubbub_init(mcif_wb30, ctx);
1677
1678 pool->mcif_wb[i] = &mcif_wb30->base;
1679 }
1680 return true;
1681 }
1682
dcn35_dsc_create(struct dc_context * ctx,uint32_t inst)1683 static struct display_stream_compressor *dcn35_dsc_create(
1684 struct dc_context *ctx, uint32_t inst)
1685 {
1686 struct dcn20_dsc *dsc =
1687 kzalloc_obj(struct dcn20_dsc);
1688
1689 if (!dsc) {
1690 BREAK_TO_DEBUGGER();
1691 return NULL;
1692 }
1693
1694 #undef REG_STRUCT
1695 #define REG_STRUCT dsc_regs
1696 dsc_regsDCN35_init(0),
1697 dsc_regsDCN35_init(1),
1698 dsc_regsDCN35_init(2),
1699 dsc_regsDCN35_init(3);
1700
1701 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1702 dsc35_set_fgcg(dsc,
1703 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1704 return &dsc->base;
1705 }
1706
dcn351_destroy_resource_pool(struct resource_pool ** pool)1707 static void dcn351_destroy_resource_pool(struct resource_pool **pool)
1708 {
1709 struct dcn351_resource_pool *dcn351_pool = TO_DCN351_RES_POOL(*pool);
1710
1711 dcn351_resource_destruct(dcn351_pool);
1712 kfree(dcn351_pool);
1713 *pool = NULL;
1714 }
1715
dcn35_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1716 static struct clock_source *dcn35_clock_source_create(
1717 struct dc_context *ctx,
1718 struct dc_bios *bios,
1719 enum clock_source_id id,
1720 const struct dce110_clk_src_regs *regs,
1721 bool dp_clk_src)
1722 {
1723 struct dce110_clk_src *clk_src =
1724 kzalloc_obj(struct dce110_clk_src);
1725
1726 if (!clk_src)
1727 return NULL;
1728
1729 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1730 regs, &cs_shift, &cs_mask)) {
1731 clk_src->base.dp_clk_src = dp_clk_src;
1732 return &clk_src->base;
1733 }
1734
1735 kfree(clk_src);
1736 BREAK_TO_DEBUGGER();
1737 return NULL;
1738 }
1739
1740 static struct dc_cap_funcs cap_funcs = {
1741 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1742 };
1743
dcn35_get_panel_config_defaults(struct dc_panel_config * panel_config)1744 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1745 {
1746 *panel_config = panel_config_defaults;
1747 }
1748
1749
dcn351_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1750 static enum dc_status dcn351_validate_bandwidth(struct dc *dc,
1751 struct dc_state *context,
1752 enum dc_validate_mode validate_mode)
1753 {
1754 bool out = false;
1755
1756 out = dml2_validate(dc, context,
1757 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1758 validate_mode);
1759
1760 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1761 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1762
1763 DC_FP_START();
1764 dcn35_decide_zstate_support(dc, context);
1765 DC_FP_END();
1766
1767 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1768 }
1769
populate_dml_pipes_from_context_fpu(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1770 static int populate_dml_pipes_from_context_fpu(struct dc *dc,
1771 struct dc_state *context,
1772 display_e2e_pipe_params_st *pipes,
1773 enum dc_validate_mode validate_mode)
1774 {
1775 int ret;
1776
1777 DC_FP_START();
1778 ret = dcn351_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1779 DC_FP_END();
1780
1781 return ret;
1782
1783 }
1784
1785 static struct resource_funcs dcn351_res_pool_funcs = {
1786 .destroy = dcn351_destroy_resource_pool,
1787 .link_enc_create = dcn35_link_encoder_create,
1788 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1789 .link_encs_assign = link_enc_cfg_link_encs_assign,
1790 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1791 .panel_cntl_create = dcn31_panel_cntl_create,
1792 .validate_bandwidth = dcn351_validate_bandwidth,
1793 .calculate_wm_and_dlg = NULL,
1794 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1795 .populate_dml_pipes = populate_dml_pipes_from_context_fpu,
1796 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1797 .release_pipe = dcn20_release_pipe,
1798 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1799 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1800 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1801 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1802 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1803 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1804 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1805 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1806 .update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu,
1807 .patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1808 .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1809 .get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia,
1810 .get_det_buffer_size = dcn31_get_det_buffer_size,
1811 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1812 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1813 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
1814 };
1815
dcn351_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn351_resource_pool * pool)1816 static bool dcn351_resource_construct(
1817 uint8_t num_virtual_links,
1818 struct dc *dc,
1819 struct dcn351_resource_pool *pool)
1820 {
1821 int i;
1822 struct dc_context *ctx = dc->ctx;
1823 struct irq_service_init_data init_data;
1824
1825 #undef REG_STRUCT
1826 #define REG_STRUCT bios_regs
1827 bios_regs_init();
1828
1829 #undef REG_STRUCT
1830 #define REG_STRUCT clk_src_regs
1831 clk_src_regs_init(0, A),
1832 clk_src_regs_init(1, B),
1833 clk_src_regs_init(2, C),
1834 clk_src_regs_init(3, D),
1835 clk_src_regs_init(4, E);
1836
1837 #undef REG_STRUCT
1838 #define REG_STRUCT abm_regs
1839 abm_regs_init(0),
1840 abm_regs_init(1),
1841 abm_regs_init(2),
1842 abm_regs_init(3);
1843
1844 #undef REG_STRUCT
1845 #define REG_STRUCT dccg_regs
1846 dccg_regs_init();
1847
1848 ctx->dc_bios->regs = &bios_regs;
1849
1850 pool->base.res_cap = &res_cap_dcn351;
1851
1852 pool->base.funcs = &dcn351_res_pool_funcs;
1853
1854 /*************************************************
1855 * Resource + asic cap harcoding *
1856 *************************************************/
1857 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1858 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1859 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1860 dc->caps.max_downscale_ratio = 600;
1861 dc->caps.i2c_speed_in_khz = 100;
1862 dc->caps.i2c_speed_in_khz_hdcp = 100;
1863 dc->caps.max_cursor_size = 256;
1864 dc->caps.min_horizontal_blanking_period = 80;
1865 dc->caps.dmdata_alloc_size = 2048;
1866 dc->caps.max_slave_planes = 3;
1867 dc->caps.max_slave_yuv_planes = 3;
1868 dc->caps.max_slave_rgb_planes = 3;
1869 dc->caps.post_blend_color_processing = true;
1870 dc->caps.force_dp_tps4_for_cp2520 = true;
1871 if (dc->config.forceHBR2CP2520)
1872 dc->caps.force_dp_tps4_for_cp2520 = false;
1873 dc->caps.dp_hpo = true;
1874 dc->caps.dp_hdmi21_pcon_support = true;
1875
1876 dc->caps.edp_dsc_support = true;
1877 dc->caps.extended_aux_timeout_support = true;
1878 dc->caps.dmcub_support = true;
1879 dc->caps.is_apu = true;
1880 dc->caps.seamless_odm = true;
1881
1882 dc->caps.zstate_support = true;
1883 dc->caps.ips_support = true;
1884 dc->caps.max_v_total = (1 << 15) - 1;
1885 dc->caps.vtotal_limited_by_fp2 = true;
1886
1887 /* Color pipeline capabilities */
1888 dc->caps.color.dpp.dcn_arch = 1;
1889 dc->caps.color.dpp.input_lut_shared = 0;
1890 dc->caps.color.dpp.icsc = 1;
1891 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1892 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1893 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1894 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1895 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1896 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1897 dc->caps.color.dpp.post_csc = 1;
1898 dc->caps.color.dpp.gamma_corr = 1;
1899 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1900
1901 dc->caps.color.dpp.hw_3d_lut = 0;
1902 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
1903 // no OGAM ROM on DCN301
1904 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1905 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1906 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1907 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1908 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1909 dc->caps.color.dpp.ocsc = 0;
1910
1911 dc->caps.color.mpc.gamut_remap = 1;
1912 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1913 dc->caps.color.mpc.ogam_ram = 1;
1914 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1915 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1916 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1917 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1918 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1919 dc->caps.color.mpc.ocsc = 1;
1920 dc->caps.color.mpc.preblend = true;
1921
1922 dc->caps.num_of_host_routers = 2;
1923 dc->caps.num_of_dpias_per_host_router = 2;
1924
1925 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1926 * to provide some margin.
1927 * It's expected for furture ASIC to have equal or higher value, in order to
1928 * have determinstic power improvement from generate to genration.
1929 * (i.e., we should not expect new ASIC generation with lower vmin rate)
1930 */
1931 dc->caps.max_disp_clock_khz_at_vmin = 650000;
1932
1933 /* Use pipe context based otg sync logic */
1934 dc->config.use_pipe_ctx_sync_logic = true;
1935
1936
1937 /* Use psp mailbox to enable assr */
1938 dc->config.use_assr_psp_message = true;
1939
1940 /* read VBIOS LTTPR caps */
1941 {
1942 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1943 enum bp_result bp_query_result;
1944 uint8_t is_vbios_lttpr_enable = 0;
1945
1946 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1947 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1948 }
1949
1950 /* interop bit is implicit */
1951 {
1952 dc->caps.vbios_lttpr_aware = true;
1953 }
1954 }
1955 dc->check_config = config_defaults;
1956
1957 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1958 dc->debug = debug_defaults_drv;
1959
1960 /*HW default is to have all the FGCG enabled, SW no need to program them*/
1961 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
1962 // Init the vm_helper
1963 if (dc->vm_helper)
1964 vm_helper_init(dc->vm_helper, 16);
1965
1966 /*************************************************
1967 * Create resources *
1968 *************************************************/
1969
1970 /* Clock Sources for Pixel Clock*/
1971 pool->base.clock_sources[DCN351_CLK_SRC_PLL0] =
1972 dcn35_clock_source_create(ctx, ctx->dc_bios,
1973 CLOCK_SOURCE_COMBO_PHY_PLL0,
1974 &clk_src_regs[0], false);
1975 pool->base.clock_sources[DCN351_CLK_SRC_PLL1] =
1976 dcn35_clock_source_create(ctx, ctx->dc_bios,
1977 CLOCK_SOURCE_COMBO_PHY_PLL1,
1978 &clk_src_regs[1], false);
1979 pool->base.clock_sources[DCN351_CLK_SRC_PLL2] =
1980 dcn35_clock_source_create(ctx, ctx->dc_bios,
1981 CLOCK_SOURCE_COMBO_PHY_PLL2,
1982 &clk_src_regs[2], false);
1983 pool->base.clock_sources[DCN351_CLK_SRC_PLL3] =
1984 dcn35_clock_source_create(ctx, ctx->dc_bios,
1985 CLOCK_SOURCE_COMBO_PHY_PLL3,
1986 &clk_src_regs[3], false);
1987 pool->base.clock_sources[DCN351_CLK_SRC_PLL4] =
1988 dcn35_clock_source_create(ctx, ctx->dc_bios,
1989 CLOCK_SOURCE_COMBO_PHY_PLL4,
1990 &clk_src_regs[4], false);
1991
1992 pool->base.clk_src_count = DCN351_CLK_SRC_TOTAL;
1993
1994 /* todo: not reuse phy_pll registers */
1995 pool->base.dp_clock_source =
1996 dcn35_clock_source_create(ctx, ctx->dc_bios,
1997 CLOCK_SOURCE_ID_DP_DTO,
1998 &clk_src_regs[0], true);
1999
2000 for (i = 0; i < pool->base.clk_src_count; i++) {
2001 if (pool->base.clock_sources[i] == NULL) {
2002 dm_error("DC: failed to create clock sources!\n");
2003 BREAK_TO_DEBUGGER();
2004 goto create_fail;
2005 }
2006 }
2007 /*temp till dml2 fully work without dml1*/
2008 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
2009
2010 /* TODO: DCCG */
2011 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2012 if (pool->base.dccg == NULL) {
2013 dm_error("DC: failed to create dccg!\n");
2014 BREAK_TO_DEBUGGER();
2015 goto create_fail;
2016 }
2017
2018 #undef REG_STRUCT
2019 #define REG_STRUCT pg_cntl_regs
2020 pg_cntl_dcn35_regs_init();
2021
2022 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
2023 if (pool->base.pg_cntl == NULL) {
2024 dm_error("DC: failed to create power gate control!\n");
2025 BREAK_TO_DEBUGGER();
2026 goto create_fail;
2027 }
2028
2029 /* TODO: IRQ */
2030 init_data.ctx = dc->ctx;
2031 pool->base.irqs = dal_irq_service_dcn351_create(&init_data);
2032 if (!pool->base.irqs)
2033 goto create_fail;
2034
2035 /* HUBBUB */
2036 pool->base.hubbub = dcn35_hubbub_create(ctx);
2037 if (pool->base.hubbub == NULL) {
2038 BREAK_TO_DEBUGGER();
2039 dm_error("DC: failed to create hubbub!\n");
2040 goto create_fail;
2041 }
2042
2043 /* DIO */
2044 pool->base.dio = dcn351_dio_create(ctx);
2045 if (pool->base.dio == NULL) {
2046 BREAK_TO_DEBUGGER();
2047 dm_error("DC: failed to create dio!\n");
2048 goto create_fail;
2049 }
2050
2051 /* HUBPs, DPPs, OPPs and TGs */
2052 for (i = 0; i < pool->base.pipe_count; i++) {
2053 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
2054 if (pool->base.hubps[i] == NULL) {
2055 BREAK_TO_DEBUGGER();
2056 dm_error(
2057 "DC: failed to create hubps!\n");
2058 goto create_fail;
2059 }
2060
2061 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2062 if (pool->base.dpps[i] == NULL) {
2063 BREAK_TO_DEBUGGER();
2064 dm_error(
2065 "DC: failed to create dpps!\n");
2066 goto create_fail;
2067 }
2068 }
2069
2070 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2071 pool->base.opps[i] = dcn35_opp_create(ctx, i);
2072 if (pool->base.opps[i] == NULL) {
2073 BREAK_TO_DEBUGGER();
2074 dm_error(
2075 "DC: failed to create output pixel processor!\n");
2076 goto create_fail;
2077 }
2078 }
2079
2080 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2081 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2082 ctx, i);
2083 if (pool->base.timing_generators[i] == NULL) {
2084 BREAK_TO_DEBUGGER();
2085 dm_error("DC: failed to create tg!\n");
2086 goto create_fail;
2087 }
2088 }
2089 pool->base.timing_generator_count = i;
2090
2091 /* PSR */
2092 pool->base.psr = dmub_psr_create(ctx);
2093 if (pool->base.psr == NULL) {
2094 dm_error("DC: failed to create psr obj!\n");
2095 BREAK_TO_DEBUGGER();
2096 goto create_fail;
2097 }
2098
2099 /* Replay */
2100 pool->base.replay = dmub_replay_create(ctx);
2101 if (pool->base.replay == NULL) {
2102 dm_error("DC: failed to create replay obj!\n");
2103 BREAK_TO_DEBUGGER();
2104 goto create_fail;
2105 }
2106
2107 /* ABM */
2108 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2109 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2110 &abm_regs[i],
2111 &abm_shift,
2112 &abm_mask);
2113 if (pool->base.multiple_abms[i] == NULL) {
2114 dm_error("DC: failed to create abm for pipe %d!\n", i);
2115 BREAK_TO_DEBUGGER();
2116 goto create_fail;
2117 }
2118 }
2119
2120 /* MPC and DSC */
2121 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2122 if (pool->base.mpc == NULL) {
2123 BREAK_TO_DEBUGGER();
2124 dm_error("DC: failed to create mpc!\n");
2125 goto create_fail;
2126 }
2127
2128 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2129 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2130 if (pool->base.dscs[i] == NULL) {
2131 BREAK_TO_DEBUGGER();
2132 dm_error("DC: failed to create display stream compressor %d!\n", i);
2133 goto create_fail;
2134 }
2135 }
2136
2137 /* DWB and MMHUBBUB */
2138 if (!dcn35_dwbc_create(ctx, &pool->base)) {
2139 BREAK_TO_DEBUGGER();
2140 dm_error("DC: failed to create dwbc!\n");
2141 goto create_fail;
2142 }
2143
2144 if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2145 BREAK_TO_DEBUGGER();
2146 dm_error("DC: failed to create mcif_wb!\n");
2147 goto create_fail;
2148 }
2149
2150 /* AUX and I2C */
2151 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2152 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2153 if (pool->base.engines[i] == NULL) {
2154 BREAK_TO_DEBUGGER();
2155 dm_error(
2156 "DC:failed to create aux engine!!\n");
2157 goto create_fail;
2158 }
2159 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2160 if (pool->base.hw_i2cs[i] == NULL) {
2161 BREAK_TO_DEBUGGER();
2162 dm_error(
2163 "DC:failed to create hw i2c!!\n");
2164 goto create_fail;
2165 }
2166 pool->base.sw_i2cs[i] = NULL;
2167 }
2168
2169 /* DCN3.5 has 6 DPIA */
2170 pool->base.usb4_dpia_count = 4;
2171 if (dc->debug.dpia_debug.bits.disable_dpia)
2172 pool->base.usb4_dpia_count = 0;
2173
2174 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2175 if (!resource_construct(num_virtual_links, dc, &pool->base,
2176 &res_create_funcs))
2177 goto create_fail;
2178
2179 /* HW Sequencer and Plane caps */
2180 dcn351_hw_sequencer_construct(dc);
2181
2182 dc->caps.max_planes = pool->base.pipe_count;
2183
2184 for (i = 0; i < dc->caps.max_planes; ++i)
2185 dc->caps.planes[i] = plane_cap;
2186
2187 dc->caps.max_odm_combine_factor = 4;
2188
2189 dc->cap_funcs = cap_funcs;
2190
2191
2192 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2193
2194 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2195 dc->dml2_options.use_native_soc_bb_construction = true;
2196 dc->dml2_options.minimize_dispclk_using_odm = false;
2197 if (dc->config.EnableMinDispClkODM)
2198 dc->dml2_options.minimize_dispclk_using_odm = true;
2199 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2200
2201 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2202 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2203
2204 dc->dml2_options.max_segments_per_hubp = 24;
2205 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2206 dc->dml2_options.override_det_buffer_size_kbytes = true;
2207
2208 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2209 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2210
2211 return true;
2212
2213 create_fail:
2214
2215 dcn351_resource_destruct(pool);
2216
2217 return false;
2218 }
2219
dcn351_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2220 struct resource_pool *dcn351_create_resource_pool(
2221 const struct dc_init_data *init_data,
2222 struct dc *dc)
2223 {
2224 struct dcn351_resource_pool *pool =
2225 kzalloc_obj(struct dcn351_resource_pool);
2226
2227 if (!pool)
2228 return NULL;
2229
2230 if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool))
2231 return &pool->base;
2232
2233 BREAK_TO_DEBUGGER();
2234 kfree(pool);
2235 return NULL;
2236 }
2237