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Searched refs:dcfclk_sta_targets (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c205 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn302_fpu_update_bw_bounding_box() local
242 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn302_fpu_update_bw_bounding_box()
244 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
246 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn302_fpu_update_bw_bounding_box()
249 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { in dcn302_fpu_update_bw_bounding_box()
250 dcfclk_sta_targets[i] = max_dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
271 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn302_fpu_update_bw_bounding_box()
283 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn302_fpu_update_bw_bounding_box()
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c201 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn303_fpu_update_bw_bounding_box() local
238 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn303_fpu_update_bw_bounding_box()
239 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
241 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn303_fpu_update_bw_bounding_box()
243 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { in dcn303_fpu_update_bw_bounding_box()
244 dcfclk_sta_targets[i] = max_dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
265 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn303_fpu_update_bw_bounding_box()
288 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn303_fpu_update_bw_bounding_box()
289 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
303 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c354 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states() local
435 entry.dcfclk_mhz = dcfclk_sta_targets[i]; in build_synthetic_soc_states()
717 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; in dcn321_update_bw_bounding_box_fpu() local
740 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn321_update_bw_bounding_box_fpu()
742 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn321_update_bw_bounding_box_fpu()
744 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn321_update_bw_bounding_box_fpu()
747 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { in dcn321_update_bw_bounding_box_fpu()
748 dcfclk_sta_targets[i] = max_dcfclk_mhz; in dcn321_update_bw_bounding_box_fpu()
770 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn321_update_bw_bounding_box_fpu()
782 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn321_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c2141 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box() local
2173 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box()
2175 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz; in dcn30_update_bw_bounding_box()
2177 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box()
2180 if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()
2181 dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz; in dcn30_update_bw_bounding_box()
2205 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn30_update_bw_bounding_box()
2228 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn30_update_bw_bounding_box()
2229 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2242 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c2812 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states() local
2893 entry.dcfclk_mhz = dcfclk_sta_targets[i]; in build_synthetic_soc_states()
3162 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in dcn32_update_bw_bounding_box_fpu() local
3179 if (min_dcfclk > dcfclk_sta_targets[0]) in dcn32_update_bw_bounding_box_fpu()
3180 dcfclk_sta_targets[0] = min_dcfclk; in dcn32_update_bw_bounding_box_fpu()
3190 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn32_update_bw_bounding_box_fpu()
3192 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn32_update_bw_bounding_box_fpu()
3194 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn32_update_bw_bounding_box_fpu()
3197 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu()
3198 dcfclk_sta_targets[i] = max_dcfclk_mhz; in dcn32_update_bw_bounding_box_fpu()
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