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Searched refs:dcc (Results 1 – 25 of 80) sorted by relevance

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/linux/Documentation/ABI/testing/
H A Ddebugfs-driver-dcc1 What: /sys/kernel/debug/dcc/.../ready
5 This file is used to check the status of the dcc
7 A 'Y' here indicates dcc is ready.
9 What: /sys/kernel/debug/dcc/.../trigger
17 What: /sys/kernel/debug/dcc/.../config_reset
22 a dcc driver to the default configuration. When '1'
27 What: /sys/kernel/debug/dcc/.../[list-number]/config
34 can be one of following dcc instructions: read,
45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config
65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config
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/linux/fs/f2fs/
H A Dsegment.c970 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in __create_discard_cmd() local
976 pend_list = &dcc->pend_list[plist_idx(len)]; in __create_discard_cmd()
992 atomic_inc(&dcc->discard_cmd_cnt); in __create_discard_cmd()
993 dcc->undiscard_blks += len; in __create_discard_cmd()
1001 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in f2fs_check_discard_tree() local
1002 struct rb_node *cur = rb_first_cached(&dcc->root), *next; in f2fs_check_discard_tree()
1029 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in __lookup_discard_cmd() local
1030 struct rb_node *node = dcc->root.rb_root.rb_node; in __lookup_discard_cmd()
1103 static void __detach_discard_cmd(struct discard_cmd_control *dcc, in __detach_discard_cmd() argument
1107 atomic_sub(dc->queued, &dcc->queued_discard); in __detach_discard_cmd()
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H A Dsegment.h1030 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in wake_up_discard_thread() local
1037 mutex_lock(&dcc->cmd_lock); in wake_up_discard_thread()
1039 if (i + 1 < dcc->discard_granularity) in wake_up_discard_thread()
1041 if (!list_empty(&dcc->pend_list[i])) { in wake_up_discard_thread()
1046 mutex_unlock(&dcc->cmd_lock); in wake_up_discard_thread()
1050 dcc->discard_wake = true; in wake_up_discard_thread()
1051 wake_up_interruptible_all(&dcc->discard_wait_queue); in wake_up_discard_thread()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
H A Ddcn201_hubp.c48 struct dc_plane_dcc_param *dcc, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c267 const struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_validate_dcc() argument
278 if (!dcc->enable) in amdgpu_dm_plane_validate_dcc()
304 if (dcc->independent_64b_blks == 0 && in amdgpu_dm_plane_validate_dcc()
317 struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers() argument
332 dcc->enable = 1; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
333 dcc->meta_pitch = afb->base.pitches[1]; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
334 dcc->independent_64b_blks = independent_64b_blks; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
337 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
339 dcc->dcc_ind_blk = hubp_ind_block_128b; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
341 dcc->dcc_ind_blk = hubp_ind_block_64b; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
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H A Damdgpu_dm_plane.h52 struct dc_plane_dcc_param *dcc,
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c376 surface->dcc.enable = false; in populate_dml21_dummy_surface_cfg()
377 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_dummy_surface_cfg()
378 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_dummy_surface_cfg()
379 surface->dcc.informative.fraction_of_zero_size_request_plane0 = 0; in populate_dml21_dummy_surface_cfg()
380 surface->dcc.informative.fraction_of_zero_size_request_plane1 = 0; in populate_dml21_dummy_surface_cfg()
442 surface->dcc.enable = plane_state->dcc.enable; in populate_dml21_surface_config_from_plane_state()
443 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_surface_config_from_plane_state()
444 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_surface_config_from_plane_state()
445 …surface->dcc.informative.fraction_of_zero_size_request_plane0 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
446 …surface->dcc.informative.fraction_of_zero_size_request_plane1 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
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/linux/drivers/bus/
H A Dvexpress-config.c108 u32 *position, u32 *dcc) in vexpress_config_get_topo() argument
116 vexpress_config_find_prop(node, "arm,vexpress,dcc", dcc); in vexpress_config_get_topo()
257 u32 site, position, dcc; in vexpress_syscfg_regmap_init() local
261 &position, &dcc); in vexpress_syscfg_regmap_init()
301 func, site, position, dcc, in vexpress_syscfg_regmap_init()
304 func->template[i] = SYS_CFGCTRL_DCC(dcc); in vexpress_syscfg_regmap_init()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
H A Ddcn30_hubp.c367 struct dc_plane_dcc_param *dcc) in hubp3_dcc_control_sienna_cichlid() argument
372 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
373 PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
374 PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c, in hubp3_dcc_control_sienna_cichlid()
375 SECONDARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
376 SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
377 SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c); in hubp3_dcc_control_sienna_cichlid()
417 struct dc_plane_dcc_param *dcc, in hubp3_program_surface_config() argument
423 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp3_program_surface_config()
425 hubp2_program_size(hubp, format, plane_size, dcc); in hubp3_program_surface_config()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn35/
H A Ddcn35_hubp.c178 struct dc_plane_dcc_param *dcc, in hubp35_program_surface_config() argument
184 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp35_program_surface_config()
186 hubp2_program_size(hubp, format, plane_size, dcc); in hubp35_program_surface_config()
H A Ddcn35_hubp.h71 struct dc_plane_dcc_param *dcc,
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zcu1275-revA.dts22 serial1 = &dcc;
37 &dcc {
H A Dzynqmp-zc1254-revA.dts22 serial1 = &dcc;
37 &dcc {
H A Dzynqmp-zc1232-revA.dts21 serial1 = &dcc;
36 &dcc {
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c167 struct dc_plane_dcc_param *dcc) in hubp1_program_size() argument
180 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
182 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp1_program_size()
185 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
190 if (!dcc->enable) { in hubp1_program_size()
562 struct dc_plane_dcc_param *dcc, in hubp1_program_surface_config() argument
566 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp1_program_surface_config()
568 hubp1_program_size(hubp, format, plane_size, dcc); in hubp1_program_surface_config()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_ggtt_fencing.c671 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle() local
682 switch (dcc & DCC_ADDRESSING_MODE_MASK) { in detect_bit_6_swizzle()
689 if (dcc & DCC_CHANNEL_XOR_DISABLE) { in detect_bit_6_swizzle()
696 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { in detect_bit_6_swizzle()
715 if (dcc == 0xffffffff) { in detect_bit_6_swizzle()
/linux/drivers/usb/typec/ucsi/
H A Ducsi_huawei_gaokun.c216 u8 dcc, ddi; in gaokun_ucsi_port_update() local
218 dcc = port_data[offset]; in gaokun_ucsi_port_update()
223 port->ccx = FIELD_GET(GAOKUN_CCX_MASK, dcc); in gaokun_ucsi_port_update()
224 port->mux = FIELD_GET(GAOKUN_MUX_MASK, dcc); in gaokun_ucsi_port_update()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c573 struct dc_plane_dcc_param *dcc) in hubp401_dcc_control() argument
578 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp401_dcc_control()
579 SECONDARY_SURFACE_DCC_EN, dcc->enable); in hubp401_dcc_control()
599 struct dc_plane_dcc_param *dcc) in hubp401_program_size() argument
635 struct dc_plane_dcc_param *dcc, in hubp401_program_surface_config() argument
641 hubp401_dcc_control(hubp, dcc); in hubp401_program_surface_config()
643 hubp401_program_size(hubp, format, plane_size, dcc); in hubp401_program_surface_config()
H A Ddcn401_hubp.h277 struct dc_plane_dcc_param *dcc);
288 struct dc_plane_dcc_param *dcc);
296 struct dc_plane_dcc_param *dcc,
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca5s.dts144 dcc {
202 temp-dcc {
H A Dvexpress-v2p-ca15-tc1.dts141 dcc {
217 temp-dcc {
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c332 struct dc_plane_dcc_param *dcc) in hubp2_program_size() argument
350 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
352 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp2_program_size()
355 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
360 if (!dcc->enable) { in hubp2_program_size()
556 struct dc_plane_dcc_param *dcc, in hubp2_program_surface_config() argument
562 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp2_program_surface_config()
564 hubp2_program_size(hubp, format, plane_size, dcc); in hubp2_program_surface_config()
/linux/drivers/s390/cio/
H A Dqdio_main.c726 int dstat, int dcc) in qdio_establish_handle_irq() argument
734 if (dcc == 1) in qdio_establish_handle_irq()
754 int cstat, dstat, rc, dcc; in qdio_int_handler() local
774 dcc = scsw_cmd_is_valid_cc(&irb->scsw) ? irb->scsw.cmd.cc : 0; in qdio_int_handler()
779 rc = qdio_establish_handle_irq(irq_ptr, cstat, dstat, dcc); in qdio_int_handler()
793 else if (dcc == 1) in qdio_int_handler()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_mall_phantom.c87 if (pipe->plane_state->dcc.enable) in dml2_helper_calculate_num_ways_for_subvp()
766 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); in enable_phantom_plane()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmem_input.h170 struct dc_plane_dcc_param *dcc,

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