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Searched refs:ctrl0 (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/crypto/bcm/
H A Dspu2.c308 /* Dump FMD ctrl0. The ctrl0 input is in host byte order */
309 static void spu2_dump_fmd_ctrl0(u64 ctrl0) in spu2_dump_fmd_ctrl0() argument
322 packet_log(" FMD CTRL0 %#16llx\n", ctrl0); in spu2_dump_fmd_ctrl0()
323 if (ctrl0 & SPU2_CIPH_ENCRYPT_EN) in spu2_dump_fmd_ctrl0()
328 ciph_type = (ctrl0 & SPU2_CIPH_TYPE) >> SPU2_CIPH_TYPE_SHIFT; in spu2_dump_fmd_ctrl0()
333 ciph_mode = (ctrl0 & SPU2_CIPH_MODE) >> SPU2_CIPH_MODE_SHIFT; in spu2_dump_fmd_ctrl0()
338 cfb = (ctrl0 & SPU2_CFB_MASK) >> SPU2_CFB_MASK_SHIFT; in spu2_dump_fmd_ctrl0()
341 proto = (ctrl0 & SPU2_PROTO_SEL) >> SPU2_PROTO_SEL_SHIFT; in spu2_dump_fmd_ctrl0()
344 if (ctrl0 in spu2_dump_fmd_ctrl0()
560 u64 ctrl0; spu2_fmd_init() local
618 u64 ctrl0 = 0; spu2_fmd_ctrl0_write() local
1191 u64 ctrl0; spu2_cipher_req_finish() local
[all...]
H A Dspu2.h76 __le64 ctrl0; member
89 /* FMD ctrl0 field masks */
/linux/drivers/input/rmi4/
H A Drmi_f01.c108 * @ctrl0: see the bit definitions above.
117 u8 ctrl0; member
412 &f01->device_control.ctrl0); in rmi_f01_probe()
422 f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_NOSLEEP_BIT; in rmi_f01_probe()
425 f01->device_control.ctrl0 |= RMI_F01_CTRL0_NOSLEEP_BIT; in rmi_f01_probe()
434 if ((f01->device_control.ctrl0 & RMI_F01_CTRL0_SLEEP_MODE_MASK) != in rmi_f01_probe()
438 f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_SLEEP_MODE_MASK; in rmi_f01_probe()
441 f01->device_control.ctrl0 |= RMI_F01_CTRL0_CONFIGURED_BIT; in rmi_f01_probe()
444 f01->device_control.ctrl0); in rmi_f01_probe()
590 f01->device_control.ctrl0); in rmi_f01_config()
[all...]
/linux/drivers/phy/samsung/
H A Dphy-exynos5250-usb2.c198 u32 ctrl0; in exynos5250_power_on() local
242 ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on()
244 ctrl0 &= ~EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK; in exynos5250_power_on()
245 ctrl0 |= drv->ref_reg_val << in exynos5250_power_on()
249 ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST | in exynos5250_power_on()
254 ctrl0 |= EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST | in exynos5250_power_on()
257 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on()
259 ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST | in exynos5250_power_on()
261 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on()
324 u32 ctrl0; in exynos5250_power_off() local
[all...]
/linux/sound/soc/codecs/
H A Dadau1977.c299 unsigned int ctrl0, ctrl0_mask; in adau1977_hw_params() local
317 ctrl0 = fs; in adau1977_hw_params()
322 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT; in adau1977_hw_params()
325 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT; in adau1977_hw_params()
367 ctrl0_mask, ctrl0); in adau1977_hw_params()
499 unsigned int ctrl0, ctrl1, drv; in adau1977_set_tdm_slot() local
549 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2; in adau1977_set_tdm_slot()
552 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4; in adau1977_set_tdm_slot()
555 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8; in adau1977_set_tdm_slot()
558 ctrl0 in adau1977_set_tdm_slot()
619 unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0; adau1977_set_dai_fmt() local
[all...]
H A Dadau17x1.c566 unsigned int ctrl0, ctrl1; in adau17x1_set_dai_fmt() local
572 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER; in adau17x1_set_dai_fmt()
576 ctrl0 = 0; in adau17x1_set_dai_fmt()
595 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; in adau17x1_set_dai_fmt()
600 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; in adau17x1_set_dai_fmt()
611 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; in adau17x1_set_dai_fmt()
617 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; in adau17x1_set_dai_fmt()
625 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL; in adau17x1_set_dai_fmt()
634 ctrl0); in adau17x1_set_dai_fmt()
/linux/drivers/media/platform/nxp/
H A Dimx-pxp.c763 u32 ctrl0; in pxp_imx6ull_data_path_ctrl0() local
765 ctrl0 = 0; in pxp_imx6ull_data_path_ctrl0()
766 ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(3); in pxp_imx6ull_data_path_ctrl0()
768 ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1); in pxp_imx6ull_data_path_ctrl0()
769 ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(3); in pxp_imx6ull_data_path_ctrl0()
771 ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0); in pxp_imx6ull_data_path_ctrl0()
773 ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(1); in pxp_imx6ull_data_path_ctrl0()
774 ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(3); in pxp_imx6ull_data_path_ctrl0()
775 ctrl0 |= BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(3); in pxp_imx6ull_data_path_ctrl0()
777 ctrl0 | in pxp_imx6ull_data_path_ctrl0()
793 u32 ctrl0; pxp_imx7d_data_path_ctrl0() local
825 u32 ctrl0; pxp_set_data_path() local
[all...]
/linux/drivers/pinctrl/intel/
H A Dpinctrl-cherryview.c630 u32 ctrl0, ctrl1; in chv_pin_dbg_show() local
633 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); in chv_pin_dbg_show()
637 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { in chv_pin_dbg_show()
642 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; in chv_pin_dbg_show()
648 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); in chv_pin_dbg_show()
809 u32 ctrl0; in chv_gpio_set_direction() local
813 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK; in chv_gpio_set_direction()
815 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; in chv_gpio_set_direction()
817 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; in chv_gpio_set_direction()
818 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); in chv_gpio_set_direction()
838 u32 ctrl0, ctrl1; chv_config_get() local
920 u32 ctrl0, pull; chv_config_set_pull() local
1102 u32 ctrl0, cfg; chv_gpio_get() local
1118 u32 ctrl0; chv_gpio_set() local
1137 u32 ctrl0, direction; chv_gpio_get_direction() local
[all...]
/linux/drivers/mmc/host/
H A Dmxs-mmc.c87 u32 ctrl0, ctrl1; in mxs_mmc_reset() local
94 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; in mxs_mmc_reset()
111 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; in mxs_mmc_reset()
115 writel(ctrl0, ssp->base + HW_SSP_CTRL0); in mxs_mmc_reset()
253 u32 ctrl0, cmd0, cmd1; in mxs_mmc_bc() local
255 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; in mxs_mmc_bc()
260 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; in mxs_mmc_bc()
264 ssp->ssp_pio_words[0] = ctrl0; in mxs_mmc_bc()
288 u32 ctrl0, cmd0, cmd1; in mxs_mmc_ac() local
297 ctrl0 in mxs_mmc_ac()
360 u32 ctrl0, cmd0, cmd1, val; mxs_mmc_adtc() local
[all...]
/linux/drivers/net/can/cc770/
H A Dcc770.c144 cc770_write_reg(priv, msgobj[mo].ctrl0, in enable_all_objs()
163 cc770_write_reg(priv, msgobj[mo].ctrl0, in enable_all_objs()
184 cc770_write_reg(priv, msgobj[mo].ctrl0, in disable_all_objs()
192 cc770_write_reg(priv, msgobj[mo].ctrl0, in disable_all_objs()
264 cc770_write_reg(priv, msgobj[mo].ctrl0, in chipset_init()
267 cc770_write_reg(priv, msgobj[mo].ctrl0, in chipset_init()
398 cc770_write_reg(priv, msgobj[mo].ctrl0, in cc770_tx()
423 cc770_write_reg(priv, msgobj[mo].ctrl0, in cc770_tx()
613 if (!(cc770_read_reg(priv, msgobj[mo].ctrl0) & in cc770_rx_interrupt()
631 cc770_write_reg(priv, msgobj[mo].ctrl0, in cc770_rx_interrupt()
644 u8 ctrl0, ctrl1; cc770_rtr_interrupt() local
[all...]
H A Dcc770.h14 u8 ctrl0; member
/linux/drivers/media/platform/raspberrypi/rp1-cfe/
H A Ddphy.c48 u32 ctrl0 = dw_csi2_host_read(dphy, DPHY_PHY_TST_CTRL0); in set_tstclr() local
50 dw_csi2_host_write(dphy, DPHY_PHY_TST_CTRL0, (ctrl0 & ~1) | val); in set_tstclr()
55 u32 ctrl0 = dw_csi2_host_read(dphy, DPHY_PHY_TST_CTRL0); in set_tstclk() local
57 dw_csi2_host_write(dphy, DPHY_PHY_TST_CTRL0, (ctrl0 & ~2) | (val << 1)); in set_tstclk()
/linux/drivers/spi/
H A Dspi-mxs.c175 u32 ctrl0; in mxs_spi_txrx_dma() local
192 ctrl0 = readl(ssp->base + HW_SSP_CTRL0); in mxs_spi_txrx_dma()
193 ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC | in mxs_spi_txrx_dma()
195 ctrl0 |= BM_SSP_CTRL0_DATA_XFER; in mxs_spi_txrx_dma()
198 ctrl0 |= BM_SSP_CTRL0_READ; in mxs_spi_txrx_dma()
210 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC; in mxs_spi_txrx_dma()
213 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT; in mxs_spi_txrx_dma()
214 ctrl0 |= min; in mxs_spi_txrx_dma()
217 dma_xfer[sg_count].pio[0] = ctrl0; in mxs_spi_txrx_dma()
/linux/drivers/thermal/
H A Darmada_thermal.c324 u32 ctrl0; in armada_select_channel() local
333 regmap_read(priv->syscon, data->syscon_control0_off, &ctrl0); in armada_select_channel()
334 ctrl0 &= ~CONTROL0_TSEN_START; in armada_select_channel()
335 regmap_write(priv->syscon, data->syscon_control0_off, ctrl0); in armada_select_channel()
338 ctrl0 &= ~(CONTROL0_TSEN_MODE_MASK << CONTROL0_TSEN_MODE_SHIFT); in armada_select_channel()
343 ctrl0 |= CONTROL0_TSEN_MODE_EXTERNAL << in armada_select_channel()
346 ctrl0 &= ~(CONTROL0_TSEN_CHAN_MASK << CONTROL0_TSEN_CHAN_SHIFT); in armada_select_channel()
347 ctrl0 |= (channel - 1) << CONTROL0_TSEN_CHAN_SHIFT; in armada_select_channel()
351 regmap_write(priv->syscon, data->syscon_control0_off, ctrl0); in armada_select_channel()
355 ctrl0 | in armada_select_channel()
[all...]
/linux/drivers/iio/proximity/
H A Dsx9310.c758 unsigned int ctrl0; in sx9310_init_compensation() local
760 ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &ctrl0); in sx9310_init_compensation()
766 ctrl0 | SX9310_REG_PROX_CTRL0_SENSOREN_MASK); in sx9310_init_compensation()
776 regmap_write(data->regmap, SX9310_REG_PROX_CTRL0, ctrl0); in sx9310_init_compensation()
944 u8 ctrl0; in sx9310_suspend() local
955 ctrl0 = data->suspend_ctrl & ~SX9310_REG_PROX_CTRL0_SENSOREN_MASK; in sx9310_suspend()
956 ret = regmap_write(data->regmap, SX9310_REG_PROX_CTRL0, ctrl0); in sx9310_suspend()
/linux/drivers/net/wireless/realtek/rtw89/
H A Dpci_be.c411 u32 ctrl0, cfg0, cfg1, dec_ctrl, idle_ltcy, act_ltcy, dis_ltcy; in rtw89_pci_ltr_set_v2() local
413 ctrl0 = rtw89_read32(rtwdev, R_BE_LTR_CTRL_0); in rtw89_pci_ltr_set_v2()
414 if (rtw89_pci_ltr_is_err_reg_val(ctrl0)) in rtw89_pci_ltr_set_v2()
437 ctrl0 |= B_BE_LTR_HW_EN; in rtw89_pci_ltr_set_v2()
441 ctrl0 &= ~B_BE_LTR_HW_EN; in rtw89_pci_ltr_set_v2()
460 rtw89_write32(rtwdev, R_BE_LTR_CTRL_0, ctrl0); in rtw89_pci_ltr_set_v2()
/linux/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_eqs.c425 u32 val, ctrl0; in get_ctrl0_val() local
438 ctrl0 = HINIC_AEQ_CTRL_0_SET(msix_entry->entry, INT_IDX) | in get_ctrl0_val()
444 val |= ctrl0; in get_ctrl0_val()
457 ctrl0 = HINIC_CEQ_CTRL_0_SET(msix_entry->entry, INTR_IDX) | in get_ctrl0_val()
464 val |= ctrl0; in get_ctrl0_val()
552 ceq_ctrl.ctrl0 = get_ctrl0_val(eq, addr); in set_ceq_ctrl_reg()
H A Dhinic_hw_dev.h330 u32 ctrl0; member
/linux/drivers/media/i2c/
H A Dds90ub953.c976 u8 ctrl0, ctrl1; in ub953_clkout_recalc_rate() local
983 ret = ub953_read(priv, UB953_REG_CLKOUT_CTRL0, &ctrl0, NULL); in ub953_clkout_recalc_rate()
998 mul = ctrl0 & 0x1f; in ub953_clkout_recalc_rate()
1009 mul = ctrl0 & 0x1f; in ub953_clkout_recalc_rate()
1010 hs_clk_div = 1 << (ctrl0 >> 5); in ub953_clkout_recalc_rate()
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_paprd.c141 static const u32 ctrl0[3] = { in ar9003_paprd_setup_single_table() local
184 REG_RMW_FIELD(ah, ctrl0[i], in ar9003_paprd_setup_single_table()
198 REG_RMW_FIELD(ah, ctrl0[i], in ar9003_paprd_setup_single_table()
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dsge.c1492 u32 wr_mid, ctrl0, op, sgl_off = 0; in cxgb4_eth_xmit() local
1693 ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) | in cxgb4_eth_xmit()
1696 ctrl0 |= TXPKT_TSTAMP_F; in cxgb4_eth_xmit()
1699 ctrl0 |= TXPKT_OVLAN_IDX_V(q->dcb_prio); in cxgb4_eth_xmit()
1701 ctrl0 |= TXPKT_T5_OVLAN_IDX_V(q->dcb_prio); in cxgb4_eth_xmit()
1703 cpl->ctrl0 = htonl(ctrl0); in cxgb4_eth_xmit()
1998 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) | in cxgb4_vf_eth_xmit()
2321 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) | in ethofld_hard_xmit()
2660 u32 ctrl0, ndes in cxgb4_selftest_lb_pkt() local
[all...]
/linux/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h1025 u32 ctrl0; member
1057 u32 ctrl0; member
/linux/drivers/net/ethernet/airoha/
H A Dairoha_regs.h924 __le32 ctrl0; member
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.c222 static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, in vbif_debugbus_read() argument
227 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_main.c6419 u32 old_ctrl0, ctrl0; in mvpp2_gmac_config() local
6423 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_config()
6427 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; in mvpp2_gmac_config()
6464 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; in mvpp2_gmac_config()
6467 if (old_ctrl0 != ctrl0) in mvpp2_gmac_config()
6468 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_config()

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