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Searched refs:control_value (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_drv.c173 u32 control_value = 0; in hibmc_set_power_mode() local
183 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL); in hibmc_set_power_mode()
184 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK | in hibmc_set_power_mode()
186 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode); in hibmc_set_power_mode()
187 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input); in hibmc_set_power_mode()
188 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL); in hibmc_set_power_mode()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_mocs.c19 u32 control_value; member
90 .control_value = __control_value, \
546 return table->table[index].control_value; in get_entry_control()
547 return table->table[table->unused_entries_index].control_value; in get_entry_control()
/linux/drivers/mmc/host/
H A Dsdhci-pci-gli.c350 u32 control_value; in gli_set_9750() local
366 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
405 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; in gli_set_9750()
406 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; in gli_set_9750()
407 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, in gli_set_9750()
409 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, in gli_set_9750()
421 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; in gli_set_9750()
422 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, in gli_set_9750()
424 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
430 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; in gli_set_9750()
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/linux/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic.h1421 u32 control_value; member
1496 u32 control_value; member