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Searched refs:cntr_mask (Results 1 – 16 of 16) sorted by relevance

/linux/arch/mips/kernel/
H A Dperf_event_mipsxx.c60 unsigned int cntr_mask; member
318 unsigned long cntr_mask; in mipsxx_pmu_alloc_counter() local
325 cntr_mask = (hwc->event_base >> 10) & 0xffff; in mipsxx_pmu_alloc_counter()
327 cntr_mask = (hwc->event_base >> 8) & 0xffff; in mipsxx_pmu_alloc_counter()
340 if (test_bit(i, &cntr_mask) && in mipsxx_pmu_alloc_counter()
709 (pev->cntr_mask & 0xffff00) | in mipspmu_perf_event_encode()
715 return (pev->cntr_mask & 0xfffc00) | in mipspmu_perf_event_encode()
718 return (pev->cntr_mask & 0xffff00) | in mipspmu_perf_event_encode()
726 if ((*mipspmu.general_event_map)[idx].cntr_mask == 0) in mipspmu_map_general_event()
753 if (pev->cntr_mask == 0) in mipspmu_map_cache_event()
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/linux/arch/x86/events/
H A Drapl.c143 unsigned int cntr_mask; member
411 if (!(rapl_pmus->cntr_mask & (1 << bit))) in rapl_pmu_event_init()
658 int num_counters = hweight32(rapl_pmus_pkg->cntr_mask); in rapl_advertise()
661 num_counters += hweight32(rapl_pmus_core->cntr_mask); in rapl_advertise()
667 if (rapl_pmus_pkg->cntr_mask & (1 << i)) { in rapl_advertise()
673 if (rapl_pmus_core && (rapl_pmus_core->cntr_mask & (1 << PERF_RAPL_CORE))) in rapl_advertise()
917 rapl_pmus_pkg->cntr_mask = perf_msr_probe(rapl_model->rapl_pkg_msrs, in rapl_pmu_init()
934 rapl_pmus_core->cntr_mask = perf_msr_probe(rapl_model->rapl_core_msrs, in rapl_pmu_init()
H A Dcore.c207 u64 cntr_mask = x86_pmu.cntr_mask64; in get_possible_counter_mask() local
211 return cntr_mask; in get_possible_counter_mask()
214 cntr_mask |= x86_pmu.hybrid_pmu[i].cntr_mask64; in get_possible_counter_mask()
216 return cntr_mask; in get_possible_counter_mask()
221 u64 cntr_mask = get_possible_counter_mask(); in reserve_pmc_hardware() local
224 for_each_set_bit(i, (unsigned long *)&cntr_mask, X86_PMC_IDX_MAX) { in reserve_pmc_hardware()
229 for_each_set_bit(i, (unsigned long *)&cntr_mask, X86_PMC_IDX_MAX) { in reserve_pmc_hardware()
238 for_each_set_bit(i, (unsigned long *)&cntr_mask, end) in reserve_pmc_hardware()
244 for_each_set_bit(i, (unsigned long *)&cntr_mask, end) in reserve_pmc_hardware()
252 u64 cntr_mask = get_possible_counter_mask(); in release_pmc_hardware() local
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H A Dperf_event.h742 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; member
855 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; member
1237 bool check_hw_exists(struct pmu *pmu, unsigned long *cntr_mask,
1845 static inline u64 intel_pmu_pebs_mask(u64 cntr_mask) in intel_pmu_pebs_mask() argument
1847 return MAX_PEBS_EVENTS_MASK & cntr_mask; in intel_pmu_pebs_mask()
/linux/drivers/perf/
H A Darm_xscale_pmu.c173 for_each_set_bit(idx, cpu_pmu->cntr_mask, XSCALE1_NUM_COUNTERS) { in xscale1pmu_handle_irq()
369 bitmap_set(cpu_pmu->cntr_mask, 0, XSCALE1_NUM_COUNTERS); in xscale1pmu_init()
505 for_each_set_bit(idx, cpu_pmu->cntr_mask, XSCALE2_NUM_COUNTERS) { in xscale2pmu_handle_irq()
724 bitmap_set(cpu_pmu->cntr_mask, 0, XSCALE2_NUM_COUNTERS); in xscale2pmu_init()
H A Darm_v7_pmu.c716 return test_bit(idx, cpu_pmu->cntr_mask); in armv7_pmnc_counter_valid()
838 for_each_set_bit(cnt, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { in armv7_pmnc_dump_regs()
912 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { in armv7pmu_handle_irq()
980 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { in armv7pmu_get_event_idx()
1035 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { in armv7pmu_reset()
1119 bitmap_set(cpu_pmu->cntr_mask, 0, nb_cnt); in armv7_read_num_pmnc_events()
1122 set_bit(ARMV7_IDX_CYCLE_COUNTER, cpu_pmu->cntr_mask); in armv7_read_num_pmnc_events()
1482 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { in krait_pmu_reset()
1506 bit += bitmap_weight(cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX); in krait_event_to_bit()
1793 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { in scorpion_pmu_reset()
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H A Darm_pmuv3.c809 for_each_andnot_bit(i, cpu_pmu->cntr_mask, cpuc->used_mask, in armv8pmu_enable_user_access()
910 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { in armv8pmu_handle_irq()
951 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { in armv8pmu_get_single_idx()
967 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { in armv8pmu_get_chain_idx()
1041 test_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask) && in armv8pmu_get_event_idx()
1168 bitmap_to_arr64(&mask, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS); in armv8pmu_reset()
1323 bitmap_set(cpu_pmu->cntr_mask, in __armv8pmu_probe_pmu()
1327 set_bit(ARMV8_PMU_CYCLE_IDX, cpu_pmu->cntr_mask); in __armv8pmu_probe_pmu()
1331 set_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask); in __armv8pmu_probe_pmu()
H A Darm_v6_pmu.c258 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV6_NUM_COUNTERS) { in armv6pmu_handle_irq()
395 bitmap_set(cpu_pmu->cntr_mask, 0, ARMV6_NUM_COUNTERS); in armv6pmu_init()
H A Darm_pmu.c756 for_each_set_bit(idx, armpmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { in cpu_pm_pmu_setup()
945 pmu->name, bitmap_weight(pmu->cntr_mask, ARMPMU_MAX_HWEVENTS), in armpmu_register()
946 ARMPMU_MAX_HWEVENTS, &pmu->cntr_mask, in armpmu_register()
H A Dapple_m1_cpu_pmu.c465 for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) { in m1_pmu_handle_irq()
651 bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); in m1_pmu_init()
/linux/arch/x86/events/amd/
H A Dcore.c437 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in __amd_put_nb_event_constraints()
549 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_alloc_nb()
742 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_check_overflow()
762 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_enable_all()
991 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_v2_handle_irq()
/linux/arch/x86/events/intel/
H A Dcore.c3421 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); in intel_pmu_reset() local
3426 if (!*(u64 *)cntr_mask) in intel_pmu_reset()
3433 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { in intel_pmu_reset()
4679 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) & in intel_pmu_hw_config() local
4683 if (cntr_mask != pebs_mask) in intel_pmu_hw_config()
5081 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_guest_get_msrs()
5114 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_pmu_enable_all()
5669 static void intel_pmu_check_counters_mask(u64 *cntr_mask, in intel_pmu_check_counters_mask() argument
5675 bit = fls64(*cntr_mask); in intel_pmu_check_counters_mask()
5679 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); in intel_pmu_check_counters_mask()
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H A Dp4.c924 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_disable_all()
1003 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_enable_all()
1045 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_handle_irq()
1399 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_init()
H A Dds.c1800 u64 cntr_mask; in intel_get_arch_pebs_data_config() local
1807 cntr_mask = (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT) | in intel_get_arch_pebs_data_config()
1810 pebs_data_cfg |= cpuc->pebs_data_cfg & cntr_mask; in intel_get_arch_pebs_data_config()
/linux/include/linux/perf/
H A Darm_pmu.h111 DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS);
/linux/arch/arm64/kvm/
H A Dpmu-emul.c1025 return bitmap_weight(arm_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS); in kvm_arm_pmu_get_max_counters()