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Searched refs:clock_limits (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c113 .clock_limits = {
230 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
232 max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz; in dcn303_fpu_update_bw_bounding_box()
234 max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
236 max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz; in dcn303_fpu_update_bw_bounding_box()
315 * dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES]. in dcn303_fpu_update_bw_bounding_box()
325 dcn3_03_soc.clock_limits[i].state = i; in dcn303_fpu_update_bw_bounding_box()
326 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn303_fpu_update_bw_bounding_box()
327 dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn303_fpu_update_bw_bounding_box()
328 dcn3_03_soc.clock_limits[ in dcn303_fpu_update_bw_bounding_box()
[all...]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c103 .clock_limits = {
185 struct _vcs_dpi_voltage_scaling_st *clock_limits = in dcn314_update_bw_bounding_box_fpu() local
186 dcn3_14_soc.clock_limits; in dcn314_update_bw_bounding_box_fpu()
218 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu()
228 clock_limits[i].state = i; in dcn314_update_bw_bounding_box_fpu()
231 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn314_update_bw_bounding_box_fpu()
233 clock_limits[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu()
235 clock_limits[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lv in dcn314_update_bw_bounding_box_fpu()
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H A Ddisplay_mode_vba_314.c2138 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c98 .clock_limits = {
267 struct _vcs_dpi_voltage_scaling_st *clock_limits = in dcn351_update_bw_bounding_box_fpu() local
268 dc->scratch.update_bw_bounding_box.clock_limits; in dcn351_update_bw_bounding_box_fpu()
292 if (dcn3_51_soc.clock_limits[j].dcfclk_mhz <= in dcn351_update_bw_bounding_box_fpu()
303 clock_limits[i].state = i; in dcn351_update_bw_bounding_box_fpu()
306 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn351_update_bw_bounding_box_fpu()
308 clock_limits[i].dcfclk_mhz < in dcn351_update_bw_bounding_box_fpu()
309 dcn3_51_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn351_update_bw_bounding_box_fpu()
311 clock_limits[i].dcfclk_mhz = in dcn351_update_bw_bounding_box_fpu()
312 dcn3_51_soc.clock_limits[closest_clk_lv in dcn351_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c119 .clock_limits = {
233 struct _vcs_dpi_voltage_scaling_st *clock_limits = in dcn35_update_bw_bounding_box_fpu() local
234 dc->scratch.update_bw_bounding_box.clock_limits; in dcn35_update_bw_bounding_box_fpu()
258 if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <= in dcn35_update_bw_bounding_box_fpu()
269 clock_limits[i].state = i; in dcn35_update_bw_bounding_box_fpu()
272 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()
274 clock_limits[i].dcfclk_mhz < in dcn35_update_bw_bounding_box_fpu()
275 dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu()
277 clock_limits[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu()
278 dcn3_5_soc.clock_limits[closest_clk_lv in dcn35_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c114 .clock_limits = {
234 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
236 max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz; in dcn302_fpu_update_bw_bounding_box()
238 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
240 max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; in dcn302_fpu_update_bw_bounding_box()
309 * dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES]. in dcn302_fpu_update_bw_bounding_box()
319 dcn3_02_soc.clock_limits[i].state = i; in dcn302_fpu_update_bw_bounding_box()
320 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn302_fpu_update_bw_bounding_box()
321 dcn3_02_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn302_fpu_update_bw_bounding_box()
322 dcn3_02_soc.clock_limits[ in dcn302_fpu_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c122 .clock_limits = {
366 .clock_limits = {
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
548 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
549 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
592 struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; in dcn31_update_bw_bounding_box()
600 memcpy(s, dcn3_1_soc.clock_limits, sizeof(dcn3_1_soc.clock_limits)); in dcn31_update_bw_bounding_box()
620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
637 dcn3_1_soc.clock_limits[closest_clk_lv in dcn31_update_bw_bounding_box()
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H A Ddisplay_mode_vba_31.c2120 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c113 .clock_limits = {
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
325 struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; in dcn301_fpu_update_bw_bounding_box()
333 memcpy(s, dcn3_01_soc.clock_limits, sizeof(dcn3_01_soc.clock_limits)); in dcn301_fpu_update_bw_bounding_box()
344 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_fpu_update_bw_bounding_box()
356 s[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn301_fpu_update_bw_bounding_box()
357 s[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn301_fpu_update_bw_bounding_box()
359 dcn3_01_soc.clock_limits[closest_clk_lv in dcn301_fpu_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c223 .clock_limits = {
334 .clock_limits = {
445 .clock_limits = {
626 .clock_limits = {
1219 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; in dcn20_calculate_dlg_params()
1220 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; in dcn20_calculate_dlg_params()
1769 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn20_calculate_wm()
1770 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn20_calculate_wm()
1792 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; in dcn20_calculate_wm()
1793 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vleve in dcn20_calculate_wm()
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H A Ddisplay_mode_vba_20.c1257 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
H A Ddisplay_mode_vba_20v2.c1317 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c126 .clock_limits = {
355 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
364 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
486 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
487 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
504 if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) { in dcn30_fpu_calculate_wm_and_dlg()
505 context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts; in dcn30_fpu_calculate_wm_and_dlg()
535 dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_update_max_clk()
537 dcn30_bb_max_clk->max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; in dcn30_fpu_update_max_clk()
539 dcn30_bb_max_clk->max_dppclk_mhz = dcn3_0_soc.clock_limits[ in dcn30_fpu_update_max_clk()
[all...]
H A Ddisplay_mode_vba_30.c1979 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c127 .clock_limits = {
197 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
1780 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz in dcn32_calculate_dlg_params()
1782 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz in dcn32_calculate_dlg_params()
2308 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
2423 * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present, in dcn32_calculate_wm_and_dlg_fpu()
2426 * DCFCLK: soc.clock_limits[2] when available in dcn32_calculate_wm_and_dlg_fpu()
2427 * UCLK: soc.clock_limits[2] when available in dcn32_calculate_wm_and_dlg_fpu()
2431 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
2437 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_tem in dcn32_calculate_wm_and_dlg_fpu()
[all...]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c377 if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel) in fetch_socbb_params()
380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
381 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
382 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()
383 mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()
395 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
396 mode_lib->vba.FabricClockPerState[i] = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()
397 mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
398 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
399 mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[ in fetch_socbb_params()
[all...]
H A Ddisplay_mode_structs.h182 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; member
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h79 struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; member
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_translation_helper.c719 out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz; in dml2_translate_soc_states()
720 out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz; in dml2_translate_soc_states()
721 out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz; in dml2_translate_soc_states()
722 out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts; in dml2_translate_soc_states()
723 out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz; in dml2_translate_soc_states()
724 out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz; in dml2_translate_soc_states()
725 out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz; in dml2_translate_soc_states()
726 out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz; in dml2_translate_soc_states()
727 out->state_array[i].phyclk_d18_mhz = dc->dml.soc.clock_limits[i].phyclk_d18_mhz; in dml2_translate_soc_states()
728 out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[ in dml2_translate_soc_states()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c139 .clock_limits = {
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c1641 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()