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Searched refs:clk_zero (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c46 cfg->clk_zero = 262000; in phy_mipi_dphy_calc_config()
138 if ((cfg->clk_prepare + cfg->clk_zero) < 300000) in phy_mipi_dphy_config_validate()
/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_20nm.c15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
H A Ddsi_phy_28nm.c723 writel(DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_28nm_dphy_set_timing()
729 if (timing->clk_zero & BIT(8)) in dsi_28nm_dphy_set_timing()
H A Ddsi_phy_28nm_8960.c473 writel(DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_28nm_dphy_set_timing()
H A Ddsi_phy_10nm.c844 writel(timing->clk_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1); in dsi_10nm_phy_enable()
H A Ddsi_phy_7nm.c1161 writel(timing->clk_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1); in dsi_7nm_phy_enable()
/linux/include/linux/phy/
H A Dphy-mipi-dphy.h100 unsigned int clk_zero; member
/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c251 (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) | in phy_meson_axg_mipi_dphy_power_on()
/linux/drivers/gpu/drm/bridge/
H A Dsamsung-dsim.c929 int clk_prepare, lpx, clk_zero, clk_post, clk_trail; in samsung_dsim_set_phy_ctrl() local
958 clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock); in samsung_dsim_set_phy_ctrl()
996 DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | in samsung_dsim_set_phy_ctrl()
H A Dnwl-dsi.c235 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero); in nwl_dsi_config_host()
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-dcphy.c315 u8 clk_zero; member
1246 val = T_CLK_ZERO(timing->clk_zero) | T_CLK_PREPARE(timing->clk_prepare); in samsung_mipi_dphy_clk_lane_timing_init()
/linux/drivers/media/i2c/
H A Dtc358746.c616 val2 = tc358746_ps_to_cnt(cfg->clk_zero, hs_byte_clk) - 1; in tc358746_apply_dphy_config()