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Searched refs:clk_values_khz (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/
H A Ddcn401_soc_and_ip_translator.c51 dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
54 dml_clk_table->dcfclk.clk_values_khz[i] = 0; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
58 dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
61 dml_clk_table->dcfclk.clk_values_khz[i] = 0; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
74 dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
77 dml_clk_table->fclk.clk_values_khz[i] = 0; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
81 dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
84 dml_clk_table->fclk.clk_values_khz[i] = 0; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
97 dml_clk_table->uclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.memclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
100 dml_clk_table->uclk.clk_values_khz[i] = 0; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/
H A Ddcn4_soc_bb.h86 .clk_values_khz = {97000},
90 .clk_values_khz = {300000, 2500000},
94 .clk_values_khz = {200000, 1564000},
98 .clk_values_khz = {100000, 2000000},
102 .clk_values_khz = {100000, 2000000},
106 .clk_values_khz = {100000, 1564000},
110 .clk_values_khz = {810000, 810000},
114 .clk_values_khz = {300000, 1200000},
118 .clk_values_khz = {666667, 666667},
122 .clk_values_khz = {625000, 625000},
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/
H A Ddml2_mcg_dcn4.c58 min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[0]; in build_min_clk_table_fine_grained()
59 min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[0]; in build_min_clk_table_fine_grained()
63 …re_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], &soc_bb->c… in build_min_clk_table_fine_grained()
76 …table->dram_bw_table.entries[i].min_fclk_khz, soc_bb->clk_table.fclk.clk_values_khz, soc_bb->clk_t… in build_min_clk_table_fine_grained()
101 …e->dram_bw_table.entries[i].min_dcfclk_khz, soc_bb->clk_table.dcfclk.clk_values_khz, soc_bb->clk_t… in build_min_clk_table_fine_grained()
138 …re_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], &soc_bb->c… in build_min_clk_table_coarse_grained()
139 min_table->dram_bw_table.entries[i].min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[i]; in build_min_clk_table_coarse_grained()
140 min_table->dram_bw_table.entries[i].min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[i]; in build_min_clk_table_coarse_grained()
179 …min_table->max_clocks_khz.dispclk = soc_bb->clk_table.dispclk.clk_values_khz[soc_bb->clk_table.dis… in build_min_clock_table()
180 …min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppcl… in build_min_clock_table()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/
H A Ddml2_dpmm_dcn4.c283 while (index < clock_table->num_clk_values && clock_table->clk_values_khz[index] < min_value) in round_up_and_copy_to_next_dpm()
287 *rounded_value = clock_table->clk_values_khz[index]; in round_up_and_copy_to_next_dpm()
290 } else if (clock_table->clk_values_khz[clock_table->num_clk_values - 1] >= min_value) { in round_up_and_copy_to_next_dpm()
347 …if (display_cfg->min_clocks.dcn4x.active.dcfclk_khz <= state_table->dcfclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
348 display_cfg->min_clocks.dcn4x.active.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
349 display_cfg->min_clocks.dcn4x.active.uclk_khz <= state_table->uclk.clk_values_khz[index]) { in map_soc_min_clocks_to_dpm_coarse_grained()
350 display_cfg->min_clocks.dcn4x.active.dcfclk_khz = state_table->dcfclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
351 display_cfg->min_clocks.dcn4x.active.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
352 display_cfg->min_clocks.dcn4x.active.uclk_khz = state_table->uclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
361 if (display_cfg->min_clocks.dcn4x.idle.dcfclk_khz <= state_table->dcfclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_wrapper.c155 …in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table… in dml21_calculate_rq_and_dlg_params()
157 …max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000; in dml21_calculate_rq_and_dlg_params()
162 …in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.… in dml21_calculate_rq_and_dlg_params()
164 …k.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000; in dml21_calculate_rq_and_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/
H A Ddml_top_soc_parameter_types.h110 unsigned long clk_values_khz[DML_MAX_CLK_TABLE_SIZE]; member
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_utils.c541 …L::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table->uclk.clk_values_khz[i]); in dml2_core_utils_get_active_min_uclk_dpm_index()
543 if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) { in dml2_core_utils_get_active_min_uclk_dpm_index()
H A Ddml2_core_dcn4.c535 if (uclk_freq_khz == soc_bb->clk_table.uclk.clk_values_khz[i]) in lookup_uclk_dpm_index_by_freq()
H A Ddml2_core_dcn4_calcs.c7137 …L::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table->uclk.clk_values_khz[i]); in get_active_min_uclk_dpm_index()
7139 if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) { in get_active_min_uclk_dpm_index()
7970 mode_lib->ms.SOCCLK = ((double)mode_lib->soc.clk_table.socclk.clk_values_khz[0] / 1000); in dml_core_mode_support()
8454 ((double)mode_lib->soc.clk_table.phyclk.clk_values_khz[0] / 1000), in dml_core_mode_support()
8455 ((double)mode_lib->soc.clk_table.phyclk_d18.clk_values_khz[0] / 1000), in dml_core_mode_support()
8456 ((double)mode_lib->soc.clk_table.phyclk_d32.clk_values_khz[0] / 1000), in dml_core_mode_support()
12038 …max_uclk_mhz = mode_lib->soc.clk_table.uclk.clk_values_khz[mode_lib->soc.clk_table.uclk.num_clk_va… in dml_core_mode_programming()