| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/ |
| H A D | dml2_mcg_dcn4.c | 50 if (soc_bb->clk_table.dcfclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
54 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
58 min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[0]; in build_min_clk_table_fine_grained()
59 min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[0]; in build_min_clk_table_fine_grained()
62 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in build_min_clk_table_fine_grained()
63 …erate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], &soc_bb->clk_t… in build_min_clk_table_fine_grained()
67 min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values; in build_min_clk_table_fine_grained()
76 …ble->dram_bw_table.entries[i].min_fclk_khz, soc_bb->clk_table.fclk.clk_values_khz, soc_bb->clk_tab… in build_min_clk_table_fine_grained()
101 …->dram_bw_table.entries[i].min_dcfclk_khz, soc_bb->clk_table.dcfclk.clk_values_khz, soc_bb->clk_ta… in build_min_clk_table_fine_grained()
137 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in build_min_clk_table_coarse_grained()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 365 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) in build_synthetic_soc_states()
366 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_synthetic_soc_states()
367 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz) in build_synthetic_soc_states()
368 max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; in build_synthetic_soc_states()
369 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz) in build_synthetic_soc_states()
370 max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; in build_synthetic_soc_states()
371 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz) in build_synthetic_soc_states()
372 max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in build_synthetic_soc_states()
373 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz) in build_synthetic_soc_states()
374 max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in build_synthetic_soc_states()
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| /linux/drivers/clk/samsung/ |
| H A D | clk-s5pv210-audss.c | 74 struct clk_hw **clk_table; in s5pv210_audss_clk_probe() local
89 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
118 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
129 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", in s5pv210_audss_clk_probe()
134 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
137 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
141 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", in s5pv210_audss_clk_probe()
147 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", in s5pv210_audss_clk_probe()
150 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", in s5pv210_audss_clk_probe()
153 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", in s5pv210_audss_clk_probe()
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| H A D | clk-exynos-audss.c | 131 struct clk_hw **clk_table; in exynos_audss_clk_probe() local
153 clk_table = clk_data->hws; in exynos_audss_clk_probe()
184 clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss", in exynos_audss_clk_probe()
195 clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s", in exynos_audss_clk_probe()
200 clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp", in exynos_audss_clk_probe()
204 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, in exynos_audss_clk_probe()
208 clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s", in exynos_audss_clk_probe()
212 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk", in exynos_audss_clk_probe()
216 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus", in exynos_audss_clk_probe()
220 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s", in exynos_audss_clk_probe()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 593 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box() local
607 ASSERT(clk_table->num_entries); in dcn31_update_bw_bounding_box()
610 for (i = 0; i < clk_table->num_entries; ++i) { in dcn31_update_bw_bounding_box()
611 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn31_update_bw_bounding_box()
612 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn31_update_bw_bounding_box()
613 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn31_update_bw_bounding_box()
614 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn31_update_bw_bounding_box()
617 for (i = 0; i < clk_table->num_entries; i++) { in dcn31_update_bw_bounding_box()
620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
629 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 232 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn35_update_bw_bounding_box_fpu() local
244 ASSERT(clk_table->num_entries); in dcn35_update_bw_bounding_box_fpu()
247 for (i = 0; i < clk_table->num_entries; ++i) { in dcn35_update_bw_bounding_box_fpu()
248 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn35_update_bw_bounding_box_fpu()
249 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn35_update_bw_bounding_box_fpu()
250 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn35_update_bw_bounding_box_fpu()
251 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn35_update_bw_bounding_box_fpu()
254 for (i = 0; i < clk_table->num_entries; i++) { in dcn35_update_bw_bounding_box_fpu()
259 clk_table->entries[i].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu()
264 if (clk_table->num_entries == 1) { in dcn35_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 266 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn351_update_bw_bounding_box_fpu() local
278 ASSERT(clk_table->num_entries); in dcn351_update_bw_bounding_box_fpu()
281 for (i = 0; i < clk_table->num_entries; ++i) { in dcn351_update_bw_bounding_box_fpu()
282 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn351_update_bw_bounding_box_fpu()
283 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn351_update_bw_bounding_box_fpu()
284 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn351_update_bw_bounding_box_fpu()
285 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn351_update_bw_bounding_box_fpu()
288 for (i = 0; i < clk_table->num_entries; i++) { in dcn351_update_bw_bounding_box_fpu()
293 clk_table->entries[i].dcfclk_mhz) { in dcn351_update_bw_bounding_box_fpu()
298 if (clk_table->num_entries == 1) { in dcn351_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 220 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn302_fpu_update_bw_bounding_box()
224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box()
225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
226 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn302_fpu_update_bw_bounding_box()
227 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn302_fpu_update_bw_bounding_box()
228 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_fpu_update_bw_bounding_box()
229 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
230 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn302_fpu_update_bw_bounding_box()
231 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn302_fpu_update_bw_bounding_box()
258 num_uclk_states = bw_params->clk_table.num_entries; in dcn302_fpu_update_bw_bounding_box()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 216 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn303_fpu_update_bw_bounding_box()
220 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn303_fpu_update_bw_bounding_box()
221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
222 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn303_fpu_update_bw_bounding_box()
223 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn303_fpu_update_bw_bounding_box()
224 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn303_fpu_update_bw_bounding_box()
225 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
226 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn303_fpu_update_bw_bounding_box()
227 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn303_fpu_update_bw_bounding_box()
252 num_uclk_states = bw_params->clk_table.num_entries; in dcn303_fpu_update_bw_bounding_box()
[all …]
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0_0_ppt.c | 641 DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table; in smu_v14_0_1_get_dpm_freq_by_index() local
643 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v14_0_1_get_dpm_freq_by_index()
648 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
650 *freq = clk_table->SocClocks[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
653 if (dpm_level >= clk_table->Vcn0ClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
655 *freq = clk_table->VClocks0[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
658 if (dpm_level >= clk_table->Vcn0ClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
660 *freq = clk_table->DClocks0[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
663 if (dpm_level >= clk_table->Vcn1ClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
665 *freq = clk_table->VClocks1[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 184 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn314_update_bw_bounding_box_fpu() local
205 ASSERT(clk_table->num_entries); in dcn314_update_bw_bounding_box_fpu()
208 for (i = 0; i < clk_table->num_entries; ++i) { in dcn314_update_bw_bounding_box_fpu()
209 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn314_update_bw_bounding_box_fpu()
210 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn314_update_bw_bounding_box_fpu()
211 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn314_update_bw_bounding_box_fpu()
212 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn314_update_bw_bounding_box_fpu()
215 for (i = 0; i < clk_table->num_entries; i++) { in dcn314_update_bw_bounding_box_fpu()
218 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu()
223 if (clk_table->num_entries == 1) { in dcn314_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 757 .clk_table = {
887 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn35_build_watermark_ranges()
890 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn35_build_watermark_ranges()
1023 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn35_clk_mgr_helper_populate_bw_params()
1083 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn35_clk_mgr_helper_populate_bw_params()
1084 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn35_clk_mgr_helper_populate_bw_params()
1087 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1088 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1089 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1092 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk; in dcn35_clk_mgr_helper_populate_bw_params()
[all …]
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| /linux/drivers/clk/mmp/ |
| H A D | clk.c | 13 struct clk **clk_table; in mmp_clk_init() local
15 clk_table = kzalloc_objs(struct clk *, nr_clks); in mmp_clk_init()
16 if (!clk_table) in mmp_clk_init()
19 unit->clk_table = clk_table; in mmp_clk_init()
21 unit->clk_data.clks = clk_table; in mmp_clk_init()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
92 unit->clk_table[clks[i].id] = clk; in mmp_register_general_gate_clks()
120 unit->clk_table[clks[i].id] = clk; in mmp_register_gate_clks()
148 unit->clk_table[clks[i].id] = clk; in mmp_register_mux_clks()
[all …]
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega10_processpptables.c | 571 phm_ppt_v1_clock_voltage_dependency_table *clk_table; in get_socclk_voltage_dependency_table() local
576 clk_table = kzalloc_flex(*clk_table, entries, in get_socclk_voltage_dependency_table()
578 if (!clk_table) in get_socclk_voltage_dependency_table()
581 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; in get_socclk_voltage_dependency_table()
584 clk_table->entries[i].vddInd = in get_socclk_voltage_dependency_table()
586 clk_table->entries[i].clk = in get_socclk_voltage_dependency_table()
590 *pp_vega10_clk_dep_table = clk_table; in get_socclk_voltage_dependency_table()
637 *clk_table; in get_gfxclk_voltage_dependency_table() local
643 clk_table = kzalloc_flex(*clk_table, entries, in get_gfxclk_voltage_dependency_table()
645 if (!clk_table) in get_gfxclk_voltage_dependency_table()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 327 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn301_fpu_update_bw_bounding_box() local
340 ASSERT(clk_table->num_entries); in dcn301_fpu_update_bw_bounding_box()
343 for (i = 0; i < clk_table->num_entries; ++i) { in dcn301_fpu_update_bw_bounding_box()
344 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn301_fpu_update_bw_bounding_box()
345 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn301_fpu_update_bw_bounding_box()
346 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn301_fpu_update_bw_bounding_box()
347 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn301_fpu_update_bw_bounding_box()
350 for (i = 0; i < clk_table->num_entries; i++) { in dcn301_fpu_update_bw_bounding_box()
353 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_fpu_update_bw_bounding_box()
360 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn301_fpu_update_bw_bounding_box()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 82 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
86 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
90 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
94 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
98 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
105 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
109 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
176 for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { in dcn401_init_single_clock()
178 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn401_init_single_clock()
185 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; in dcn401_build_wm_range_table()
[all …]
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_5_ppt.c | 635 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_5_get_dpm_level_count() local
639 *count = clk_table->NumSocClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
642 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
645 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
648 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
651 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
665 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_5_get_dpm_freq_by_index() local
667 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_5_get_dpm_freq_by_index()
672 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
674 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
[all …]
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| H A D | smu_v13_0_4_ppt.c | 434 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_4_get_dpm_freq_by_index() local
436 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_4_get_dpm_freq_by_index()
441 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
443 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
446 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
448 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
451 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
453 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
457 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
459 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in smu_v13_0_4_get_dpm_freq_by_index()
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| H A D | yellow_carp_ppt.c | 769 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in yellow_carp_get_dpm_level_count() local
773 *count = clk_table->NumSocClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
776 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
779 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
782 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
785 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
799 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in yellow_carp_get_dpm_freq_by_index() local
801 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
806 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
808 *freq = clk_table->SocClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 194 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
195 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
205 …e.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfcl… in dcn32_build_wm_range_table_fpu()
207 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()
208 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; in dcn32_build_wm_range_table_fpu()
246 …params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memcl… in dcn32_build_wm_range_table_fpu()
248 …params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memcl… in dcn32_build_wm_range_table_fpu()
250 …params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memcl… in dcn32_build_wm_range_table_fpu()
252 …params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memcl… in dcn32_build_wm_range_table_fpu()
2517 …int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_l… in dcn32_calculate_wm_and_dlg_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 98 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
134 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
140 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
145 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
151 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
156 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
161 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
271 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
369 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_min_memclk()
372 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn3_set_hard_min_memclk()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu15/ |
| H A D | smu_v15_0_0_ppt.c | 719 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v15_0_0_get_dpm_freq_by_index() local
721 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v15_0_0_get_dpm_freq_by_index()
726 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
728 *freq = clk_table->SocClocks[dpm_level]; in smu_v15_0_0_get_dpm_freq_by_index()
731 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
733 *freq = clk_table->VClocks[dpm_level]; in smu_v15_0_0_get_dpm_freq_by_index()
736 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
738 *freq = clk_table->DClocks[dpm_level]; in smu_v15_0_0_get_dpm_freq_by_index()
742 if (dpm_level >= clk_table->NumMemPstatesEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
744 *freq = clk_table->MemPstateTable[dpm_level].MemClk; in smu_v15_0_0_get_dpm_freq_by_index()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in vg_build_watermark_ranges()
412 bw_params->clk_table.entries[i].dcfclk_mhz; in vg_build_watermark_ranges()
493 .clk_table = {
597 bw_params->clk_table.num_entries = j + 1; in vg_clk_mgr_helper_populate_bw_params()
599 for (i = 0; i < bw_params->clk_table.num_entries - 1; i++, j--) { in vg_clk_mgr_helper_populate_bw_params()
600 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
601 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
602 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; in vg_clk_mgr_helper_populate_bw_params()
603 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfP… in vg_clk_mgr_helper_populate_bw_params()
606 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; in vg_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/clk/hisilicon/ |
| H A D | clk.c | 31 struct clk **clk_table; in hisi_clk_alloc() local
45 clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, in hisi_clk_alloc()
46 sizeof(*clk_table), in hisi_clk_alloc()
48 if (!clk_table) in hisi_clk_alloc()
51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
62 struct clk **clk_table; in hisi_clk_init() local
76 clk_table = kzalloc_objs(*clk_table, nr_clks); in hisi_clk_init()
77 if (!clk_table) in hisi_clk_init()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 264 .clk_table = {
371 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn316_build_watermark_ranges()
374 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn316_build_watermark_ranges()
511 bw_params->clk_table.num_entries = j + 1; in dcn316_clk_mgr_helper_populate_bw_params()
522 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in dcn316_clk_mgr_helper_populate_bw_params()
525 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; in dcn316_clk_mgr_helper_populate_bw_params()
526 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn316_clk_mgr_helper_populate_bw_params()
527 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; in dcn316_clk_mgr_helper_populate_bw_params()
530 bw_params->clk_table.entries[i].wck_ratio = 2; in dcn316_clk_mgr_helper_populate_bw_params()
533 bw_params->clk_table.entries[i].wck_ratio = 4; in dcn316_clk_mgr_helper_populate_bw_params()
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