| /linux/drivers/clk/meson/ |
| H A D | axg-audio.c | 381 static struct clk_regmap ddr_arb =
383 static struct clk_regmap pdm =
385 static struct clk_regmap tdmin_a =
387 static struct clk_regmap tdmin_b =
389 static struct clk_regmap tdmin_c =
391 static struct clk_regmap tdmin_lb =
393 static struct clk_regmap tdmout_a =
395 static struct clk_regmap tdmout_b =
397 static struct clk_regmap tdmout_c =
399 static struct clk_regmap frddr_a =
[all …]
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| H A D | a1-peripherals.c | 49 static struct clk_regmap a1_xtal_in = {
64 static struct clk_regmap a1_fixpll_in = {
79 static struct clk_regmap a1_usb_phy_in = {
94 static struct clk_regmap a1_usb_ctrl_in = {
109 static struct clk_regmap a1_hifipll_in = {
124 static struct clk_regmap a1_syspll_in = {
139 static struct clk_regmap a1_dds_in = {
154 static struct clk_regmap a1_rtc_32k_in = {
180 static struct clk_regmap a1_rtc_32k_div = {
219 static struct clk_regmap a1_rtc_32k_xtal = {
[all …]
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| H A D | axg.c | 111 static struct clk_regmap axg_fixed_pll_dco = {
154 static struct clk_regmap axg_fixed_pll = {
175 static struct clk_regmap axg_sys_pll_dco = {
213 static struct clk_regmap axg_sys_pll = {
272 static struct clk_regmap axg_gp0_pll_dco = {
318 static struct clk_regmap axg_gp0_pll = {
344 static struct clk_regmap axg_hifi_pll_dco = {
391 static struct clk_regmap axg_hifi_pll = {
420 static struct clk_regmap axg_fclk_div2 = {
447 static struct clk_regmap axg_fclk_div3 = {
[all …]
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| H A D | vclk.c | 12 clk_get_meson_vclk_gate_data(struct clk_regmap *clk) in clk_get_meson_vclk_gate_data()
19 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_gate_enable()
33 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_gate_disable()
41 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_gate_is_enabled()
58 clk_get_meson_vclk_div_data(struct clk_regmap *clk) in clk_get_meson_vclk_div_data()
66 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_div_recalc_rate()
76 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_div_determine_rate()
86 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_div_set_rate()
102 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_div_enable()
114 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_div_disable()
[all …]
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| H A D | c3-pll.c | 37 static struct clk_regmap c3_fclk_50m_en = {
78 static struct clk_regmap c3_fclk_div2 = {
106 static struct clk_regmap c3_fclk_div2p5 = {
134 static struct clk_regmap c3_fclk_div3 = {
162 static struct clk_regmap c3_fclk_div4 = {
190 static struct clk_regmap c3_fclk_div5 = {
218 static struct clk_regmap c3_fclk_div7 = {
246 static struct clk_regmap c3_gp0_pll_dco = {
303 static struct clk_regmap c3_gp0_pll = {
329 static struct clk_regmap c3_hifi_pll_dco = {
[all …]
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| H A D | meson8b.c | 122 static struct clk_regmap meson8b_fixed_pll_dco = {
167 static struct clk_regmap meson8b_fixed_pll = {
238 static struct clk_regmap meson8b_hdmi_pll_dco = {
285 static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
303 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
321 static struct clk_regmap meson8b_sys_pll_dco = {
362 static struct clk_regmap meson8b_sys_pll = {
393 static struct clk_regmap meson8b_fclk_div2 = {
421 static struct clk_regmap meson8b_fclk_div3 = {
449 static struct clk_regmap meson8b_fclk_div4 = {
[all …]
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| H A D | clk-phase.c | 16 meson_clk_phase_data(struct clk_regmap *clk) in meson_clk_phase_data()
39 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_get_phase()
50 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_set_phase()
77 meson_clk_triphase_data(struct clk_regmap *clk) in meson_clk_triphase_data()
84 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_sync()
103 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_get_phase()
115 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_set_phase()
141 meson_sclk_ws_inv_data(struct clk_regmap *clk) in meson_sclk_ws_inv_data()
148 struct clk_regmap *clk = to_clk_regmap(hw); in meson_sclk_ws_inv_sync()
166 struct clk_regmap *clk = to_clk_regmap(hw); in meson_sclk_ws_inv_get_phase()
[all …]
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| H A D | s4-pll.c | 54 static struct clk_regmap s4_fixed_pll_dco = {
97 static struct clk_regmap s4_fixed_pll = {
129 static struct clk_regmap s4_fclk_div2 = {
155 static struct clk_regmap s4_fclk_div3 = {
181 static struct clk_regmap s4_fclk_div4 = {
207 static struct clk_regmap s4_fclk_div5 = {
233 static struct clk_regmap s4_fclk_div7 = {
261 static struct clk_regmap s4_fclk_div2p5 = {
293 static struct clk_regmap s4_gp0_pll_dco = {
334 static struct clk_regmap s4_gp0_pll = {
[all …]
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| H A D | sclk-div.c | 26 meson_sclk_div_data(struct clk_regmap *clk) in meson_sclk_div_data()
102 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_determine_rate()
112 static void sclk_apply_ratio(struct clk_regmap *clk, in sclk_apply_ratio()
128 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_set_duty_cycle()
142 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_get_duty_cycle()
158 static void sclk_apply_divider(struct clk_regmap *clk, in sclk_apply_divider()
170 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_set_rate()
185 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_recalc_rate()
193 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_enable()
203 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_disable()
[all …]
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| H A D | g12a-aoclk.c | 71 static struct clk_regmap g12a_ao_cts_oscin = {
98 static struct clk_regmap g12a_ao_32k_by_oscin_pre = {
113 static struct clk_regmap g12a_ao_32k_by_oscin_div = {
152 static struct clk_regmap g12a_ao_32k_by_oscin_sel = {
171 static struct clk_regmap g12a_ao_32k_by_oscin = {
189 static struct clk_regmap g12a_ao_cec_pre = {
204 static struct clk_regmap g12a_ao_cec_div = {
243 static struct clk_regmap g12a_ao_cec_sel = {
262 static struct clk_regmap g12a_ao_cec = {
278 static struct clk_regmap g12a_ao_cts_rtc_oscin = {
[all …]
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| H A D | clk-regmap.h | 24 struct clk_regmap { struct
30 static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) in to_clk_regmap() argument
32 return container_of(hw, struct clk_regmap, hw); in to_clk_regmap()
55 clk_get_regmap_gate_data(struct clk_regmap *clk) in clk_get_regmap_gate_data()
83 clk_get_regmap_div_data(struct clk_regmap *clk) in clk_get_regmap_div_data()
113 clk_get_regmap_mux_data(struct clk_regmap *clk) in clk_get_regmap_mux_data()
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| H A D | axg-aoclk.c | 51 static struct clk_regmap axg_ao_cts_oscin = {
66 static struct clk_regmap axg_ao_32k_pre = {
91 static struct clk_regmap axg_ao_32k_div = {
130 static struct clk_regmap axg_ao_32k_sel = {
149 static struct clk_regmap axg_ao_32k = {
165 static struct clk_regmap axg_ao_cts_rtc_oscin = {
184 static struct clk_regmap axg_ao_clk81 = {
209 static struct clk_regmap axg_ao_saradc_mux = {
226 static struct clk_regmap axg_ao_saradc_div = {
243 static struct clk_regmap axg_ao_saradc_gate = {
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| H A D | clk-regmap.c | 14 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_init()
55 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_endisable()
77 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_is_enabled()
107 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_div_recalc_rate()
126 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_div_determine_rate()
151 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_div_set_rate()
185 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_mux_get_parent()
201 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_mux_set_parent()
213 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_mux_determine_rate()
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| H A D | gxbb-aoclk.c | 39 static struct clk_regmap gxbb_ao_cts_oscin = {
54 static struct clk_regmap gxbb_ao_32k_pre = {
77 static struct clk_regmap gxbb_ao_32k_div = {
114 static struct clk_regmap gxbb_ao_32k_sel = {
133 static struct clk_regmap gxbb_ao_32k = {
147 static struct clk_regmap gxbb_ao_cts_rtc_oscin = {
169 static struct clk_regmap gxbb_ao_clk81 = {
188 static struct clk_regmap gxbb_ao_cts_cec = {
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| H A D | a1-pll.c | 29 static struct clk_regmap a1_fixed_pll_dco = {
72 static struct clk_regmap a1_fixed_pll = {
100 static struct clk_regmap a1_hifi_pll = {
164 static struct clk_regmap a1_fclk_div2 = {
202 static struct clk_regmap a1_fclk_div3 = {
235 static struct clk_regmap a1_fclk_div5 = {
268 static struct clk_regmap a1_fclk_div7 = {
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| H A D | clk-cpu-dyndiv.c | 14 meson_clk_cpu_dyndiv_data(struct clk_regmap *clk) in meson_clk_cpu_dyndiv_data()
22 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_recalc_rate()
33 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_determine_rate()
42 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_set_rate()
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| H A D | clk-pll.c | 40 meson_clk_pll_data(struct clk_regmap *clk) in meson_clk_pll_data()
75 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_recalc_rate()
249 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_determine_rate()
279 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_wait_lock()
296 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_is_enabled()
312 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_init()
358 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_enable()
403 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_disable()
421 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_pll_set_rate()
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| H A D | clk-mpll.c | 26 meson_clk_mpll_data(struct clk_regmap *clk) in meson_clk_mpll_data()
78 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_recalc_rate()
92 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_determine_rate()
112 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_set_rate()
129 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_init()
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| H A D | c3-peripherals.c | 60 static struct clk_regmap c3_rtc_xtal_clkin = {
80 static struct clk_regmap c3_rtc_32k_div = {
124 static struct clk_regmap c3_rtc_32k_sel = {
139 static struct clk_regmap c3_rtc_32k = {
161 static struct clk_regmap c3_rtc_clk = {
331 static struct clk_regmap c3_clk_12_24m_in = {
346 static struct clk_regmap c3_clk_12_24m = {
363 static struct clk_regmap c3_fclk_25m_div = {
379 static struct clk_regmap c3_fclk_25m = {
417 static struct clk_regmap c3_gen_sel = {
[all …]
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| H A D | meson-clkc-utils.h | 31 struct clk_regmap _name = { \
54 struct clk_regmap _prefix##_name##_sel = { \
73 struct clk_regmap _prefix##_name##_div = { \
92 struct clk_regmap _prefix##_name = { \
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| H A D | clk-dualdiv.c | 31 meson_clk_dualdiv_data(struct clk_regmap *clk) in meson_clk_dualdiv_data()
50 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_dualdiv_recalc_rate()
92 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_dualdiv_determine_rate()
111 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_dualdiv_set_rate()
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| /linux/drivers/clk/qcom/ |
| H A D | clk-regmap.h | 20 struct clk_regmap { struct
28 static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) in to_clk_regmap() argument
30 return container_of(hw, struct clk_regmap, hw); in to_clk_regmap()
36 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
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| H A D | clk-regmap-phy-mux.c | 18 static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr) in to_clk_regmap_phy_mux()
25 struct clk_regmap *clkr = to_clk_regmap(hw); in phy_mux_is_enabled()
39 struct clk_regmap *clkr = to_clk_regmap(hw); in phy_mux_enable()
49 struct clk_regmap *clkr = to_clk_regmap(hw); in phy_mux_disable()
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| H A D | clk-regmap.c | 24 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_is_enabled_regmap()
50 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_enable_regmap()
74 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_disable_regmap()
97 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk) in devm_clk_register_regmap()
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| H A D | clk-cbf-8996.c | 95 struct clk_regmap clkr;
98 static struct clk_cbf_8996_mux *to_clk_cbf_8996_mux(struct clk_regmap *clkr) in to_clk_cbf_8996_mux()
108 struct clk_regmap *clkr = to_clk_regmap(hw); in clk_cbf_8996_mux_get_parent()
119 struct clk_regmap *clkr = to_clk_regmap(hw); in clk_cbf_8996_mux_set_parent()
205 static struct clk_regmap *cbf_msm8996_clks[] = {
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