Home
last modified time | relevance | path

Searched refs:clk_index (Results 1 – 8 of 8) sorted by relevance

/linux/sound/soc/fsl/
H A Dfsl_asrc.c393 u32 clk_index[2], div[2]; in fsl_asrc_config_pair()
471 clk_index[IN] = asrc_priv->clk_map[IN][config->inclk]; in fsl_asrc_config_pair()
472 clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk]; in fsl_asrc_config_pair()
475 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; in fsl_asrc_config_pair()
489 inrate, clk_index[ideal ? OUT : IN]); in fsl_asrc_config_pair()
495 clk = asrc_priv->asrck_clk[clk_index[OUT]]; in fsl_asrc_config_pair()
505 outrate, clk_index[OUT]); in fsl_asrc_config_pair()
532 ASRCSR_AICS(index, clk_index[IN]) | in fsl_asrc_config_pair()
533 ASRCSR_AOCS(index, clk_index[OUT])); in fsl_asrc_config_pair()
675 int clk_rate, clk_index; in fsl_asrc_select_clk()
387 u32 clk_index[2], div[2]; fsl_asrc_config_pair() local
669 int clk_rate, clk_index; fsl_asrc_select_clk() local
[all...]
/linux/drivers/clk/bcm/
H A Dclk-kona.c864 if (sel->clk_index == BAD_CLK_INDEX) { in __sel_commit()
872 sel->clk_index = index; in __sel_commit()
877 BUG_ON((u32)sel->clk_index >= sel->parent_count); in __sel_commit()
878 parent_sel = sel->parent_sel[sel->clk_index]; in __sel_commit()
927 previous = sel->clk_index; in selector_write()
931 sel->clk_index = index; in selector_write()
942 sel->clk_index = previous; /* Revert the change */ in selector_write()
H A Dclk-kona.h338 u8 clk_index; /* current selected index in parent_sel[] */ member
347 .clk_index = BAD_CLK_INDEX, \
/linux/drivers/phy/ti/
H A Dphy-j721e-wiz.c811 const struct wiz_clk_mux_sel *mux_sel, int clk_index) in wiz_mux_clk_register() argument
836 output_clk_names[clk_index]); in wiz_mux_clk_register()
843 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]); in wiz_mux_clk_register()
863 wiz->output_clks[clk_index] = clk; in wiz_mux_clk_register()
1052 int clk_index; in wiz_clock_register() local
1056 clk_index = TI_WIZ_PLL0_REFCLK; in wiz_clock_register()
1057 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { in wiz_clock_register()
1058 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); in wiz_clock_register()
1060 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]); in wiz_clock_register()
/linux/drivers/phy/cadence/
H A Dphy-cadence-sierra.c757 int clk_index) in cdns_sierra_pll_mux_register() argument
769 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]); in cdns_sierra_pll_mux_register()
775 init->parent_data = pll_mux_parent_data[clk_index]; in cdns_sierra_pll_mux_register()
788 sp->clk_data.hws[clk_index] = &mux->hw; in cdns_sierra_pll_mux_register()
790 sp->pll_clks[clk_index] = devm_clk_hw_get_clk(dev, &mux->hw, in cdns_sierra_pll_mux_register()
791 clk_names[clk_index]); in cdns_sierra_pll_mux_register()
802 int ret = 0, i, clk_index; in cdns_sierra_phy_register_pll_mux() local
804 clk_index = CDNS_SIERRA_PLL_CMNLC; in cdns_sierra_phy_register_pll_mux()
805 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) { in cdns_sierra_phy_register_pll_mux()
811 termen_field, clk_index); in cdns_sierra_phy_register_pll_mux()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c1214 int clk_index = 0; in navi10_is_support_fine_grained_dpm() local
1216 clk_index = smu_cmn_to_asic_specific_index(smu, in navi10_is_support_fine_grained_dpm()
1219 if (clk_index < 0) in navi10_is_support_fine_grained_dpm()
1220 return clk_index; in navi10_is_support_fine_grained_dpm()
1222 dpm_desc = &pptable->DpmDescriptor[clk_index]; in navi10_is_support_fine_grained_dpm()
H A Dsienna_cichlid_ppt.c1248 uint32_t clk_index = 0; in sienna_cichlid_is_support_fine_grained_dpm() local
1251 clk_index = smu_cmn_to_asic_specific_index(smu, in sienna_cichlid_is_support_fine_grained_dpm()
1254 dpm_desc = &table_member[clk_index]; in sienna_cichlid_is_support_fine_grained_dpm()
/linux/drivers/gpu/drm/amd/pm/
H A Damdgpu_pm.c854 uint clk_index; in amdgpu_get_pp_od_clk_voltage() local
860 for (clk_index = 0 ; clk_index < 6 ; clk_index++) { in amdgpu_get_pp_od_clk_voltage()
861 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); in amdgpu_get_pp_od_clk_voltage()