Searched refs:clk_gen (Results 1 – 3 of 3) sorted by relevance
107 u32 clk_gen; /* divider for spi output clock generated by the controller */ member 367 mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen); in mchp_corespi_set_clk_gen() 444 unsigned long clk_hz, spi_hz, clk_gen; in mchp_corespi_calculate_clkgen() local 459 * clk_gen is the register name for the clock divider on MPFS. in mchp_corespi_calculate_clkgen() 461 clk_gen = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; in mchp_corespi_calculate_clkgen() 462 if (clk_gen > CLK_GEN_MODE1_MAX || clk_gen <= CLK_GEN_MIN) { in mchp_corespi_calculate_clkgen() 463 clk_gen = DIV_ROUND_UP(clk_hz, spi_hz); in mchp_corespi_calculate_clkgen() 464 clk_gen = fls(clk_gen) in mchp_corespi_calculate_clkgen() [all...]
52 uint64_t clk_gen:1; member 68 uint64_t clk_gen:1;96 uint64_t clk_gen:1; member 112 uint64_t clk_gen:1;359 uint64_t clk_gen:1; member 375 uint64_t clk_gen:1;
67 * enum clk_gen - GEN#0/GEN#1 clock schemes72 enum clk_gen { enum