Searched refs:clk_div_mask (Results 1 – 11 of 11) sorted by relevance
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()55 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate()91 val &= ~(clk_div_mask(div->width) << div->shift); in clk_divider_gate_set_rate()137 val &= clk_div_mask(div->width); in clk_divider_disable()150 val &= clk_div_mask(div->width); in clk_divider_is_enabled()210 val &= clk_div_mask(width); in imx_clk_hw_divider_gate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()44 div_value &= clk_div_mask(PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()95 val = orig & ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()96 (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); in imx8m_clk_composite_divider_set_rate()122 prediv_value &= clk_div_mask(divider->width); in imx8m_divider_determine_rate()126 div_value &= clk_div_mask(PCG_DIV_WIDTH); in imx8m_divider_determine_rate()
124 val &= ~(clk_div_mask(divider->width) << divider->shift); in imx93_clk_composite_divider_set_rate()
48 unsigned int maxdiv = 0, mask = clk_div_mask(width); in _get_table_maxdiv()72 return clk_div_mask(width); in _get_maxdiv()74 return 1 << clk_div_mask(width); in _get_maxdiv()76 return 2 * (clk_div_mask(width) + 1); in _get_maxdiv()79 return clk_div_mask(width) + 1; in _get_maxdiv()101 return val ? val : clk_div_mask(width) + 1; in _get_div()128 return (div == clk_div_mask(width) + 1) ? 0 : div; in _get_val()162 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()444 val &= clk_div_mask(divider->width); in clk_divider_determine_rate()468 return min_t(unsigned int, value, clk_div_mask(width)); in divider_get_val()[all …]
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()399 val &= clk_div_mask(divider->width); in m10v_clk_divider_determine_rate()429 val &= ~(clk_div_mask(divider->width) << divider->shift); in m10v_clk_divider_set_rate()
602 val &= clk_div_mask(div->width); in bm1880_clk_div_recalc_rate()622 val &= clk_div_mask(div->width); in bm1880_clk_div_determine_rate()652 val &= ~(clk_div_mask(div->width) << div_hw->div.shift); in bm1880_clk_div_set_rate()
118 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()138 val &= clk_div_mask(div->width); in clk_regmap_div_determine_rate()163 clk_div_mask(div->width) << div->shift, val); in clk_regmap_div_set_rate()
155 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()157 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()260 val &= clk_div_mask(cfg->width); in mpfs_cfg_clk_recalc_rate()286 mask = clk_div_mask(cfg->width) << cfg->shift; in mpfs_cfg_clk_set_rate()
81 mult &= clk_div_mask(MPFS_CCC_FBDIV_WIDTH); in mpfs_ccc_pll_recalc_rate()83 ref_div &= clk_div_mask(MPFS_CCC_REFDIV_WIDTH); in mpfs_ccc_pll_recalc_rate()
103 return (reg >> div->shift) & clk_div_mask(div->width); in sg2044_div_get_reg_div()168 reg &= ~(clk_div_mask(div->width) << div->shift); in sg2044_div_set_reg_div()
723 #define clk_div_mask(width) ((1 << (width)) - 1) macro