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Searched refs:clk_ctrl (Results 1 – 25 of 38) sorted by relevance

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/linux/arch/mips/ath79/
H A Dclock.c238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
307 clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_clocks_init()
309 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
312 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) in ar934x_clocks_init()
314 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) in ar934x_clocks_init()
319 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
322 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_clocks_init()
324 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) in ar934x_clocks_init()
329 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
332 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) in ar934x_clocks_init()
[all …]
/linux/drivers/clk/aspeed/
H A Dclk-ast2700.c623 struct ast2700_clk_ctrl *clk_ctrl) in ast2700_clk_hw_register_fixed_display() argument
629 val = readl(clk_ctrl->base + SCU0_CLK_SEL2); in ast2700_clk_hw_register_fixed_display()
641 return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, 0, (xdclk * mult) / div); in ast2700_clk_hw_register_fixed_display()
646 struct ast2700_clk_ctrl *clk_ctrl) in ast2700_clk_hw_register_hpll() argument
651 val = readl(clk_ctrl->base + SCU0_HWSTRAP1); in ast2700_clk_hw_register_hpll()
652 if ((readl(clk_ctrl->base) & REVISION_ID) && (val & BIT(3))) { in ast2700_clk_hw_register_hpll()
655 return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, in ast2700_clk_hw_register_hpll()
658 return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, in ast2700_clk_hw_register_hpll()
661 return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, in ast2700_clk_hw_register_hpll()
664 return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, in ast2700_clk_hw_register_hpll()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_1_7_msm8996.h69 .clk_ctrl = DPU_CLK_CTRL_VIG0,
77 .clk_ctrl = DPU_CLK_CTRL_VIG1,
85 .clk_ctrl = DPU_CLK_CTRL_VIG2,
93 .clk_ctrl = DPU_CLK_CTRL_VIG3,
101 .clk_ctrl = DPU_CLK_CTRL_RGB0,
109 .clk_ctrl = DPU_CLK_CTRL_RGB1,
117 .clk_ctrl = DPU_CLK_CTRL_RGB2,
125 .clk_ctrl = DPU_CLK_CTRL_RGB3,
133 .clk_ctrl = DPU_CLK_CTRL_DMA0,
141 .clk_ctrl = DPU_CLK_CTRL_DMA1,
H A Ddpu_5_0_sm8150.h75 .clk_ctrl = DPU_CLK_CTRL_VIG0,
83 .clk_ctrl = DPU_CLK_CTRL_VIG1,
91 .clk_ctrl = DPU_CLK_CTRL_VIG2,
99 .clk_ctrl = DPU_CLK_CTRL_VIG3,
107 .clk_ctrl = DPU_CLK_CTRL_DMA0,
115 .clk_ctrl = DPU_CLK_CTRL_DMA1,
123 .clk_ctrl = DPU_CLK_CTRL_DMA2,
131 .clk_ctrl = DPU_CLK_CTRL_DMA3,
281 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_6_0_sm8250.h74 .clk_ctrl = DPU_CLK_CTRL_VIG0,
82 .clk_ctrl = DPU_CLK_CTRL_VIG1,
90 .clk_ctrl = DPU_CLK_CTRL_VIG2,
98 .clk_ctrl = DPU_CLK_CTRL_VIG3,
106 .clk_ctrl = DPU_CLK_CTRL_DMA0,
114 .clk_ctrl = DPU_CLK_CTRL_DMA1,
122 .clk_ctrl = DPU_CLK_CTRL_DMA2,
130 .clk_ctrl = DPU_CLK_CTRL_DMA3,
318 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_7_0_sm8350.h74 .clk_ctrl = DPU_CLK_CTRL_VIG0,
82 .clk_ctrl = DPU_CLK_CTRL_VIG1,
90 .clk_ctrl = DPU_CLK_CTRL_VIG2,
98 .clk_ctrl = DPU_CLK_CTRL_VIG3,
106 .clk_ctrl = DPU_CLK_CTRL_DMA0,
114 .clk_ctrl = DPU_CLK_CTRL_DMA1,
122 .clk_ctrl = DPU_CLK_CTRL_DMA2,
130 .clk_ctrl = DPU_CLK_CTRL_DMA3,
291 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_4_0_sdm845.h72 .clk_ctrl = DPU_CLK_CTRL_VIG0,
80 .clk_ctrl = DPU_CLK_CTRL_VIG1,
88 .clk_ctrl = DPU_CLK_CTRL_VIG2,
96 .clk_ctrl = DPU_CLK_CTRL_VIG3,
104 .clk_ctrl = DPU_CLK_CTRL_DMA0,
112 .clk_ctrl = DPU_CLK_CTRL_DMA1,
120 .clk_ctrl = DPU_CLK_CTRL_DMA2,
128 .clk_ctrl = DPU_CLK_CTRL_DMA3,
H A Ddpu_4_1_sdm670.h31 .clk_ctrl = DPU_CLK_CTRL_VIG0,
39 .clk_ctrl = DPU_CLK_CTRL_VIG0,
47 .clk_ctrl = DPU_CLK_CTRL_DMA0,
55 .clk_ctrl = DPU_CLK_CTRL_DMA1,
63 .clk_ctrl = DPU_CLK_CTRL_DMA2,
H A Ddpu_5_1_sc8180x.h75 .clk_ctrl = DPU_CLK_CTRL_VIG0,
83 .clk_ctrl = DPU_CLK_CTRL_VIG1,
91 .clk_ctrl = DPU_CLK_CTRL_VIG2,
99 .clk_ctrl = DPU_CLK_CTRL_VIG3,
107 .clk_ctrl = DPU_CLK_CTRL_DMA0,
115 .clk_ctrl = DPU_CLK_CTRL_DMA1,
123 .clk_ctrl = DPU_CLK_CTRL_DMA2,
131 .clk_ctrl = DPU_CLK_CTRL_DMA3,
287 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_8_1_sm8450.h74 .clk_ctrl = DPU_CLK_CTRL_VIG0,
82 .clk_ctrl = DPU_CLK_CTRL_VIG1,
90 .clk_ctrl = DPU_CLK_CTRL_VIG2,
98 .clk_ctrl = DPU_CLK_CTRL_VIG3,
106 .clk_ctrl = DPU_CLK_CTRL_DMA0,
114 .clk_ctrl = DPU_CLK_CTRL_DMA1,
122 .clk_ctrl = DPU_CLK_CTRL_DMA2,
130 .clk_ctrl = DPU_CLK_CTRL_DMA3,
304 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_5_3_sm6150.h69 .clk_ctrl = DPU_CLK_CTRL_VIG0,
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
85 .clk_ctrl = DPU_CLK_CTRL_DMA1,
93 .clk_ctrl = DPU_CLK_CTRL_DMA2,
101 .clk_ctrl = DPU_CLK_CTRL_DMA3,
159 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_8_4_sa8775p.h73 .clk_ctrl = DPU_CLK_CTRL_VIG0,
81 .clk_ctrl = DPU_CLK_CTRL_VIG1,
89 .clk_ctrl = DPU_CLK_CTRL_VIG2,
97 .clk_ctrl = DPU_CLK_CTRL_VIG3,
105 .clk_ctrl = DPU_CLK_CTRL_DMA0,
113 .clk_ctrl = DPU_CLK_CTRL_DMA1,
121 .clk_ctrl = DPU_CLK_CTRL_DMA2,
129 .clk_ctrl = DPU_CLK_CTRL_DMA3,
311 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_8_0_sc8280xp.h73 .clk_ctrl = DPU_CLK_CTRL_VIG0,
81 .clk_ctrl = DPU_CLK_CTRL_VIG1,
89 .clk_ctrl = DPU_CLK_CTRL_VIG2,
97 .clk_ctrl = DPU_CLK_CTRL_VIG3,
105 .clk_ctrl = DPU_CLK_CTRL_DMA0,
113 .clk_ctrl = DPU_CLK_CTRL_DMA1,
121 .clk_ctrl = DPU_CLK_CTRL_DMA2,
129 .clk_ctrl = DPU_CLK_CTRL_DMA3,
H A Ddpu_6_2_sc7180.h55 .clk_ctrl = DPU_CLK_CTRL_VIG0,
63 .clk_ctrl = DPU_CLK_CTRL_DMA0,
71 .clk_ctrl = DPU_CLK_CTRL_DMA1,
79 .clk_ctrl = DPU_CLK_CTRL_DMA2,
154 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_6_4_sm6350.h62 .clk_ctrl = DPU_CLK_CTRL_VIG0,
70 .clk_ctrl = DPU_CLK_CTRL_DMA0,
78 .clk_ctrl = DPU_CLK_CTRL_DMA1,
86 .clk_ctrl = DPU_CLK_CTRL_DMA2,
148 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_5_2_sm7150.h72 .clk_ctrl = DPU_CLK_CTRL_VIG0,
80 .clk_ctrl = DPU_CLK_CTRL_VIG1,
88 .clk_ctrl = DPU_CLK_CTRL_DMA0,
96 .clk_ctrl = DPU_CLK_CTRL_DMA1,
104 .clk_ctrl = DPU_CLK_CTRL_DMA2,
247 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_1_15_msm8917.h53 .clk_ctrl = DPU_CLK_CTRL_VIG0,
61 .clk_ctrl = DPU_CLK_CTRL_RGB0,
69 .clk_ctrl = DPU_CLK_CTRL_RGB1,
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_1_14_msm8937.h53 .clk_ctrl = DPU_CLK_CTRL_VIG0,
61 .clk_ctrl = DPU_CLK_CTRL_RGB0,
69 .clk_ctrl = DPU_CLK_CTRL_RGB1,
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_1_16_msm8953.h53 .clk_ctrl = DPU_CLK_CTRL_VIG0,
61 .clk_ctrl = DPU_CLK_CTRL_RGB0,
69 .clk_ctrl = DPU_CLK_CTRL_RGB1,
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_5_4_sm6125.h69 .clk_ctrl = DPU_CLK_CTRL_VIG0,
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
85 .clk_ctrl = DPU_CLK_CTRL_DMA1,
138 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_6_5_qcm2290.h44 .clk_ctrl = DPU_CLK_CTRL_VIG0,
52 .clk_ctrl = DPU_CLK_CTRL_DMA0,
/linux/include/linux/platform_data/
H A Dnet-cw1200.h19 int (*clk_ctrl)(const struct cw1200_platform_data_spi *pdata, member
34 int (*clk_ctrl)(const struct cw1200_platform_data_sdio *pdata, member
/linux/drivers/net/wireless/st/cw1200/
H A Dcw1200_sdio.c194 if (pdata->clk_ctrl) in cw1200_sdio_off()
195 pdata->clk_ctrl(pdata, false); in cw1200_sdio_off()
228 if (pdata->clk_ctrl) { in cw1200_sdio_on()
229 if (pdata->clk_ctrl(pdata, true)) { in cw1200_sdio_on()
H A Dcw1200_spi.c290 if (pdata->clk_ctrl) in cw1200_spi_off()
291 pdata->clk_ctrl(pdata, false); in cw1200_spi_off()
313 if (pdata->clk_ctrl) { in cw1200_spi_on()
314 if (pdata->clk_ctrl(pdata, true)) { in cw1200_spi_on()
/linux/sound/soc/codecs/
H A Dadau1372.c795 unsigned int clk_ctrl = ADAU1372_CLK_CTRL_MCLK_EN; in adau1372_set_power() local
822 clk_ctrl |= ADAU1372_CLK_CTRL_CLKSRC; in adau1372_set_power()
826 ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_CLKSRC, clk_ctrl); in adau1372_set_power()
934 unsigned int clk_ctrl; in adau1372_probe() local
971 clk_ctrl = ADAU1372_CLK_CTRL_CC_MDIV; in adau1372_probe()
974 clk_ctrl = 0; in adau1372_probe()
977 clk_ctrl = 0; in adau1372_probe()
991 regmap_update_bits(regmap, ADAU1372_REG_CLK_CTRL, ADAU1372_CLK_CTRL_CC_MDIV, clk_ctrl); in adau1372_probe()

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