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Searched refs:cfgBIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_7_0_offset.h3137 #define cfgBIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 macro
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H A Dnbio_7_2_0_offset.h3524 #define cfgBIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 macro
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