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Searched refs:cfg (Results 1 – 25 of 2144) sorted by relevance

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/linux/tools/testing/selftests/drivers/net/
H A Dping.py14 def _test_v4(cfg) -> None: argument
15 if not cfg.addr_v["4"]:
18 cmd("ping -c 1 -W0.5 " + cfg.remote_addr_v["4"])
19 cmd("ping -c 1 -W0.5 " + cfg.addr_v["4"], host=cfg.remote)
20 cmd("ping -s 65000 -c 1 -W0.5 " + cfg.remote_addr_v["4"])
21 cmd("ping -s 65000 -c 1 -W0.5 " + cfg.addr_v["4"], host=cfg.remote)
23 def _test_v6(cfg) -> None: argument
24 if not cfg.addr_v["6"]:
27 cmd("ping -c 1 -W5 " + cfg.remote_addr_v["6"])
28 cmd("ping -c 1 -W5 " + cfg.addr_v["6"], host=cfg.remote)
[all …]
H A Dpsp.py28 def _send_with_ack(cfg, msg): argument
29 cfg.comm_sock.send(msg)
30 response = cfg.comm_sock.recv(4)
35 def _remote_read_len(cfg): argument
36 cfg.comm_sock.send(b'read len\0')
37 return int(cfg.comm_sock.recv(1024)[:-1].decode('utf-8'))
40 def _make_clr_conn(cfg, ipver=None): argument
41 _send_with_ack(cfg, b'conn clr\0')
42 remote_addr = cfg.remote_addr_v[ipver] if ipver else cfg.remote_addr
43 s = socket.create_connection((remote_addr, cfg.comm_port), )
[all …]
H A Dshaper.py10 def get_shapers(cfg, nl_shaper) -> None: argument
12 shapers = nl_shaper.get({'ifindex': cfg.ifindex}, dump=True)
21 def get_caps(cfg, nl_shaper) -> None: argument
23 caps = nl_shaper.cap_get({'ifindex': cfg.ifindex}, dump=True)
33 def set_qshapers(cfg, nl_shaper) -> None: argument
35 caps = nl_shaper.cap_get({'ifindex': cfg.ifindex,
44 cfg.queues = True;
46 channels = netnl.channels_get({'header': {'dev-index': cfg.ifindex}})
48 cfg.rx_type = 'rx'
49 cfg.nr_queues = channels['rx-count']
[all …]
H A Dhds.py14 def _get_hds_mode(cfg, netnl) -> str: argument
16 rings = netnl.rings_get({'header': {'dev-index': cfg.ifindex}})
24 def _xdp_onoff(cfg): argument
25 prog = cfg.net_lib_dir / "xdp_dummy.bpf.o"
27 (cfg.ifname, prog))
28 ip("link set dev %s xdp off" % cfg.ifname)
31 def _ioctl_ringparam_modify(cfg, netnl) -> None: argument
37 rings = netnl.rings_get({'header': {'dev-index': cfg.ifindex}})
51 def get_hds(cfg, netnl) -> None: argument
52 _get_hds_mode(cfg, netnl)
[all …]
/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
42 cfg->clk_prepare = 38000; in phy_mipi_dphy_calc_config()
43 cfg->clk_settle = 95000; in phy_mipi_dphy_calc_config()
44 cfg->clk_term_en = 0; in phy_mipi_dphy_calc_config()
45 cfg->clk_trail = 60000; in phy_mipi_dphy_calc_config()
46 cfg->clk_zero = 262000; in phy_mipi_dphy_calc_config()
[all …]
/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.c22 u32 cfg; in gsc_wait_reset() local
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
26 if (!cfg) in gsc_wait_reset()
36 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
38 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
40 cfg |= GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
42 cfg &= ~GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
43 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
48 u32 cfg; in gsc_hw_set_gsc_irq_enable() local
50 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.c21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
28 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
29 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL); in fimc_hw_reset()
30 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
33 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
34 cfg &= ~FIMC_REG_CIGCTRL_SWRST; in fimc_hw_reset()
35 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
[all …]
H A Dfimc-lite-reg.c23 u32 cfg; in flite_hw_reset() local
25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
26 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
27 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
30 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
31 if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY) in flite_hw_reset()
36 cfg |= FLITE_REG_CIGCTRL_SWRST; in flite_hw_reset()
37 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
42 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq() local
43 cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM; in flite_hw_clear_pending_irq()
[all …]
/linux/tools/testing/selftests/drivers/net/hw/
H A Drss_api.py18 def _require_2qs(cfg): argument
25 def _ethtool_create(cfg, act, opts): argument
32 def _ethtool_get_cfg(cfg, fl_type, to_nl=False): argument
64 def test_rxfh_nl_set_fail(cfg): argument
68 _require_2qs(cfg)
78 ethnl.rss_set({"header": {"dev-index": cfg.ifindex},
84 def test_rxfh_nl_set_indir(cfg): argument
88 qcnt = _require_2qs(cfg)
91 reset = defer(cfg.ethnl.rss_set,
92 {"header": {"dev-index": cfg.ifindex}, "indir": None})
[all …]
H A Drss_ctx.py24 def _rss_key_check(cfg, data=None, context=0): argument
26 data = get_rss(cfg, context=context)
33 def get_rss(cfg, context=0): argument
37 def get_drop_err_sum(cfg): argument
38 stats = ip("-s -s link show dev " + cfg.ifname, json=True)[0]
47 def ethtool_create(cfg, act, opts): argument
54 def require_ntuple(cfg): argument
62 def require_context_cnt(cfg, need_cnt): argument
66 if need_cnt and cfg.context_cnt and cfg.context_cnt < need_cnt:
72 def _get_rx_cnts(cfg, prev=None): argument
[all …]
H A Dtso.py36 def run_one_stream(cfg, ipver, remote_v4, remote_v6, should_lso): argument
37 cfg.require_cmd("socat", local=False, remote=True)
42 with bkg(listen_cmd, host=cfg.remote, exit_wait=True) as nc:
43 wait_port_listen(port, host=cfg.remote)
57 qstat_old = cfg.netnl.qstats_get({"ifindex": cfg.ifindex}, dump=True)[0]
61 qstat_new = cfg.netnl.qstats_get({"ifindex": cfg.ifindex}, dump=True)[0]
66 total_lso_wire = len(buf) * 0.90 // cfg.dev["mtu"]
67 total_lso_super = len(buf) * 0.90 // cfg.dev["tso_max_size"]
75 if cfg.have_stat_super_count:
80 if cfg.have_stat_wire_count:
[all …]
H A Dcsum.py12 def test_receive(cfg, ipver="6", extra_args=None): argument
14 if not cfg.have_rx_csum:
24 cmd(tx_cmd, host=cfg.remote)
27 def test_transmit(cfg, ipver="6", extra_args=None): argument
29 if (not cfg.have_tx_csum_generic and
30 not (cfg.have_tx_csum_ipv4 and ipver == "4") and
31 not (cfg.have_tx_csum_ipv6 and ipver == "6")):
43 with bkg(rx_cmd, host=cfg.remote, exit_wait=True):
44 wait_port_listen(34000, proto="udp", host=cfg.remote)
48 def test_builder(name, cfg, ipver="6", tx=False, extra_args=""): argument
[all …]
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.c18 u32 cfg; in camif_hw_reset() local
20 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
21 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
22 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
25 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
26 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
28 cfg |= CIGCTRL_IRQ_LEVEL; in camif_hw_reset()
29 camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg); in camif_hw_reset()
32 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
33 cfg &= ~CIGCTRL_SWRST; in camif_hw_reset()
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_config.h60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
63 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
67 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
68 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
69 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) argument
70 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) argument
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_config.h121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) argument
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) argument
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) argument
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) argument
129 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val argument
131 #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs) argument
132 #define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr) argument
[all …]
/linux/drivers/pci/
H A Decam.c32 struct pci_config_window *cfg; in pci_ecam_create() local
40 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); in pci_ecam_create()
41 if (!cfg) in pci_ecam_create()
48 cfg->parent = dev; in pci_ecam_create()
49 cfg->ops = ops; in pci_ecam_create()
50 cfg->busr.start = busr->start; in pci_ecam_create()
51 cfg->busr.end = busr->end; in pci_ecam_create()
52 cfg->busr.flags = IORESOURCE_BUS; in pci_ecam_create()
53 cfg->bus_shift = bus_shift; in pci_ecam_create()
54 bus_range = resource_size(&cfg->busr); in pci_ecam_create()
[all …]
/linux/sound/hda/common/
H A Dauto_parser.c56 static void add_auto_cfg_input_pin(struct hda_codec *codec, struct auto_pin_cfg *cfg, in add_auto_cfg_input_pin() argument
59 if (cfg->num_inputs < AUTO_CFG_MAX_INS) { in add_auto_cfg_input_pin()
60 cfg->inputs[cfg->num_inputs].pin = nid; in add_auto_cfg_input_pin()
61 cfg->inputs[cfg->num_inputs].type = type; in add_auto_cfg_input_pin()
62 cfg->inputs[cfg->num_inputs].has_boost_on_pin = in add_auto_cfg_input_pin()
64 cfg->num_inputs++; in add_auto_cfg_input_pin()
173 struct auto_pin_cfg *cfg, in snd_hda_parse_pin_defcfg() argument
179 struct auto_out_pin line_out[ARRAY_SIZE(cfg->line_out_pins)]; in snd_hda_parse_pin_defcfg()
180 struct auto_out_pin speaker_out[ARRAY_SIZE(cfg->speaker_pins)]; in snd_hda_parse_pin_defcfg()
181 struct auto_out_pin hp_out[ARRAY_SIZE(cfg->hp_pins)]; in snd_hda_parse_pin_defcfg()
[all …]
/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8998.c283 struct hdmi_8998_phy_pll_reg_cfg *cfg) in pll_calculate() argument
330 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
332 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
334 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
335 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
336 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
337 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
338 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
339 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
340 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
[all …]
H A Dhdmi_phy_8996.c219 struct hdmi_8996_phy_pll_reg_cfg *cfg) in pll_calculate() argument
286 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
288 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
290 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
291 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
292 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
293 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
294 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
295 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
296 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
[all …]
/linux/arch/x86/pci/
H A Dmmconfig-shared.c38 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) in pci_mmconfig_remove() argument
40 if (cfg->res.parent) in pci_mmconfig_remove()
41 release_resource(&cfg->res); in pci_mmconfig_remove()
42 list_del(&cfg->list); in pci_mmconfig_remove()
43 kfree(cfg); in pci_mmconfig_remove()
48 struct pci_mmcfg_region *cfg, *tmp; in free_all_mmcfg() local
51 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list) in free_all_mmcfg()
52 pci_mmconfig_remove(cfg); in free_all_mmcfg()
57 struct pci_mmcfg_region *cfg; in list_add_sorted() local
60 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) { in list_add_sorted()
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.c133 u64 cfg, last; in rpm_lmac_tx_enable() local
138 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_tx_enable()
139 last = cfg; in rpm_lmac_tx_enable()
141 cfg |= RPM_TX_EN; in rpm_lmac_tx_enable()
143 cfg &= ~(RPM_TX_EN); in rpm_lmac_tx_enable()
145 if (cfg != last) in rpm_lmac_tx_enable()
146 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); in rpm_lmac_tx_enable()
153 u64 cfg; in rpm_lmac_rx_tx_enable() local
158 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_rx_tx_enable()
160 cfg |= RPM_RX_EN | RPM_TX_EN; in rpm_lmac_rx_tx_enable()
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_config.h56 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
57 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
58 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
59 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
60 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
61 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
63 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
64 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
65 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) argument
66 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) argument
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_gsc.c66 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) argument
381 u32 cfg; in gsc_sw_reset() local
385 cfg = (GSC_SW_RESET_SRESET); in gsc_sw_reset()
386 gsc_write(cfg, GSC_SW_RESET); in gsc_sw_reset()
390 cfg = gsc_read(GSC_SW_RESET); in gsc_sw_reset()
391 if (!cfg) in gsc_sw_reset()
396 if (cfg) { in gsc_sw_reset()
402 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
403 cfg |= (GSC_IN_BASE_ADDR_MASK | in gsc_sw_reset()
405 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
[all …]
H A Dexynos_drm_fimc.c139 u32 cfg; in fimc_sw_reset() local
142 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
143 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
164 u32 cfg; in fimc_set_type_ctrl() local
166 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
167 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | in fimc_set_type_ctrl()
174 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | in fimc_set_type_ctrl()
179 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
184 u32 cfg; in fimc_handle_jpeg() local
188 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_handle_jpeg()
[all …]
/linux/drivers/infiniband/hw/ionic/
H A Dionic_lif_cfg.c30 void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg) in ionic_fill_lif_cfg() argument
34 cfg->lif = lif; in ionic_fill_lif_cfg()
35 cfg->hwdev = &lif->ionic->pdev->dev; in ionic_fill_lif_cfg()
36 cfg->lif_index = lif->index; in ionic_fill_lif_cfg()
37 cfg->lif_hw_index = lif->hw_index; in ionic_fill_lif_cfg()
39 cfg->dbid = lif->kern_pid; in ionic_fill_lif_cfg()
40 cfg->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); in ionic_fill_lif_cfg()
41 cfg->dbpage = lif->kern_dbpage; in ionic_fill_lif_cfg()
42 cfg->intr_ctrl = lif->ionic->idev.intr_ctrl; in ionic_fill_lif_cfg()
44 cfg->db_phys = lif->ionic->bars[IONIC_PCI_BAR_DBELL].bus_addr; in ionic_fill_lif_cfg()
[all …]

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