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Searched refs:cdclk (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c167 u8 (*calc_voltage_level)(int cdclk);
173 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
180 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
187 return display->funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
191 int cdclk) in intel_cdclk_calc_voltage_level() argument
193 return display->funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
199 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
205 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
211 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
217 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
[all …]
H A Dintel_cdclk.h19 unsigned int cdclk, vco, ref, bypass; member
57 …to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->cdclk.…
59 …to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->cdclk.…
H A Dskl_prefill.c90 return prefill_adjust(prefill_lines_nocdclk(ctx), ctx->adj.cdclk); in prefill_lines_cdclk()
103 ctx->adj.cdclk = intel_cdclk_prefill_adjustment_worst(crtc_state); in skl_prefill_init_worst()
113 ctx->adj.cdclk = intel_cdclk_prefill_adjustment(crtc_state); in skl_prefill_init()
H A Dskl_prefill.h26 unsigned int cdclk; member
H A Dhsw_ips.c230 if (min_cdclk > display->cdclk.max_cdclk_freq) in hsw_ips_min_cdclk()
248 if (_hsw_ips_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq) in hsw_ips_compute_config()
H A Dintel_dsi.c68 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_dsi_mode_valid()
H A Dintel_flipq.c149 DIV_ROUND_UP(display->cdclk.hw.cdclk * cdclk_factor(display), 540000) + in intel_flipq_exec_time_us()
H A Dintel_backlight.c1115 clock = KHz(display->cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1133 clock = KHz(display->cdclk.hw.cdclk); in i965_hz_to_pwm()
H A Dintel_dvo.c228 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_dvo_mode_valid()
H A Dintel_lvds.c400 int max_pixclk = display->cdclk.max_dotclk_freq; in intel_lvds_mode_valid()
H A Dintel_crt.c357 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_crt_mode_valid()
H A Dintel_fbc.c1731 if (_intel_fbc_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq) { in intel_fbc_check_plane()
1757 if (min_cdclk > display->cdclk.max_cdclk_freq) in intel_fbc_min_cdclk()
H A Dskl_scaler.c1092 return min(max_scale, DIV_ROUND_UP_ULL((u64)display->cdclk.max_dotclk_freq << 16, in _skl_scaler_max_scale()
H A Dintel_dp.c912 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) / in bigjoiner_bw_max_bpp()
1013 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100)) in intel_dp_dsc_get_slice_count()
1354 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq || in intel_dp_needs_joiner()
1409 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_dp_mode_valid()
H A Dintel_tv.c964 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_tv_mode_valid()
H A Dintel_display_power_well.c1040 intel_cdclk_clock_changed(&display->cdclk.hw, in gen9_disable_dc_states()
H A Dintel_display.c2383 int clock_limit = display->cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2399 clock_limit = display->cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
2407 clock_limit = display->cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
8011 int max_dotclock = display->cdclk.max_dotclk_freq; in max_dotclock()
H A Dintel_dp_mst.c1423 int max_dotclk = display->cdclk.max_dotclk_freq; in mst_connector_mode_valid_ctx()
H A Dintel_sdvo.c1945 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_sdvo_mode_valid()
H A Dskl_watermark.c3035 dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); in skl_wm_get_hw_state()
/linux/drivers/clk/samsung/
H A Dclk-s5pv210-audss.c75 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
110 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
124 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
125 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
H A Dclk-exynos-audss.c129 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
189 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
191 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
192 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
/linux/arch/arm/boot/dts/samsung/
H A Ds3c64xx-pinctrl.dtsi334 i2s0_cdclk: i2s0-cdclk-pins {
346 i2s1_cdclk: i2s1-cdclk-pins {
360 i2s2_cdclk: i2s2-cdclk-pins {
/linux/drivers/gpu/drm/i915/
H A Di915_reg.h1127 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ argument
1128 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \