Home
last modified time | relevance | path

Searched refs:caches (Results 1 – 25 of 165) sorted by relevance

1234567

/linux/kernel/bpf/
H A Dmemalloc.c577 ma->caches = pcc; in bpf_mem_alloc_init()
589 ma->caches = pcc; in bpf_mem_alloc_percpu_init()
611 pcc = ma->caches; in bpf_mem_alloc_percpu_unit_init()
674 if (ma->caches) { in check_leaked_objs()
676 cc = per_cpu_ptr(ma->caches, cpu); in check_leaked_objs()
692 free_percpu(ma->caches); in free_mem_alloc_no_barrier()
694 ma->caches = NULL; in free_mem_alloc_no_barrier()
768 if (ma->caches) { in bpf_mem_alloc_destroy()
771 cc = per_cpu_ptr(ma->caches, cpu); in bpf_mem_alloc_destroy()
910 ret = unit_alloc(this_cpu_ptr(ma->caches)->cache + idx); in bpf_mem_alloc()
[all …]
/linux/tools/cgroup/
H A Dmemcg_slabinfo.py183 caches = {}
202 caches[addr] = cache
214 for addr in caches:
216 cache_show(caches[addr], cfg, stats[addr])
/linux/Documentation/filesystems/
H A D9p.rst136 cache=mode specifies a caching policy. By default, no caches are used.
142 0b00000000 all caches disabled, mmap disabled
143 0b00000001 file caches enabled
144 0b00000010 meta-data caches enabled
146 0b00001000 loose caches (no explicit consistency with server)
156 loose 0b00001111 (non-coherent file and meta-data caches)
164 IMPORTANT: loose caches (and by extension at the moment fscache)
240 /sys/fs/9p/caches. (applies only to cache=fscache)
/linux/arch/arm/boot/compressed/
H A Dhead-xscale.S28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
30 @ disabling MMU and caches
H A Dhead-sa1100.S38 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
40 @ disabling MMU and caches
/linux/Documentation/block/
H A Dwriteback_cache_control.rst9 write back caches. That means the devices signal I/O completion to the
52 For devices that do not support volatile write caches there is no driver
57 For devices with volatile write caches the driver needs to tell the block layer
58 that it supports flushing caches by setting the
/linux/arch/arm/mm/
H A Dproc-arm720.S51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
117 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
145 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
H A Dproc-sa110.S51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
169 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
H A Dproc-fa526.S41 mcr p15, 0, r0, c1, c0, 0 @ disable caches
61 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
143 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm926.S55 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
413 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
426 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
434 mov r0, #4 @ disable write-back on caches explicitly
H A Dproc-sa1100.S59 mcr p15, 0, r0, c1, c0, 0 @ disable caches
76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
208 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-mohawk.S46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
367 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
386 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
H A Dproc-arm920.S63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
397 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
410 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm925.S86 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
444 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
451 mov r0, #4 @ disable write-back on caches explicitly
H A Dproc-arm740.S51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
H A Dproc-arm1022.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm922.S65 mcr p15, 0, r0, c1, c0, 0 @ disable caches
82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
387 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm1026.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
407 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm1020e.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
425 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
/linux/Documentation/core-api/real-time/
H A Dhardware.rst20 Main memory and the associated caches are the most common shared resources among
21 tasks in a system. One task can dominate the available caches, forcing another
24 size of the caches available. Larger caches may reduce stalls because more lines
34 Avoiding shared L2 or L3 caches is not always possible. Even when cache sharing
/linux/tools/perf/
H A Dbuiltin-stat.c1302 struct cpu_cache_level caches[MAX_CACHE_LVL]; in cpu__get_cache_details() local
1308 ret = build_caches_for_cpu(cpu.cpu, caches, &caches_cnt); in cpu__get_cache_details()
1332 if (caches[i].level > caches[max_level_index].level) in cpu__get_cache_details()
1336 cache->cache_lvl = caches[max_level_index].level; in cpu__get_cache_details()
1337 cache->cache = cpu__get_cache_id_from_map(cpu, caches[max_level_index].map); in cpu__get_cache_details()
1345 if (caches[i].level == cache_level) { in cpu__get_cache_details()
1347 cache->cache = cpu__get_cache_id_from_map(cpu, caches[i].map); in cpu__get_cache_details()
1350 cpu_cache_level__free(&caches[i]); in cpu__get_cache_details()
1358 cpu_cache_level__free(&caches[i++]); in cpu__get_cache_details()
1655 struct cpu_cache_level *caches = env->caches; in perf_env__get_cache_id_for_cpu() local
[all …]
/linux/drivers/acpi/numa/
H A Dhmat.c73 struct list_head caches; member
131 list_for_each_entry(tcache, &target->caches, node) { in hmat_get_extended_linear_cache_size()
232 INIT_LIST_HEAD(&target->caches); in alloc_target()
545 list_add_tail(&tcache->node, &target->caches); in hmat_parse_cache()
849 list_for_each_entry(tcache, &target->caches, node) in hmat_register_target_cache()
1013 list_for_each_entry_safe(tcache, cnext, &target->caches, node) { in hmat_free_structures()
/linux/arch/openrisc/
H A DKconfig90 bool "Have write through data caches"
93 Select this if your implementation features write through data caches.
95 caches at relevant times. Most OpenRISC implementations support write-
96 through data caches.
/linux/Documentation/filesystems/nfs/
H A Drpc-cache.rst13 a wide variety of values to be caches.
15 There are a number of caches that are similar in structure though
17 of common code for managing these caches.
19 Examples of caches that are likely to be needed are:
105 includes it on a list of caches that will be regularly
/linux/tools/perf/util/
H A Dheader.c1207 int build_caches_for_cpu(u32 cpu, struct cpu_cache_level caches[], u32 *cntp) in build_caches_for_cpu() argument
1224 if (cpu_cache_level__cmp(&c, &caches[i])) in build_caches_for_cpu()
1229 caches[*cntp] = c; in build_caches_for_cpu()
1238 static int build_caches(struct cpu_cache_level caches[], u32 *cntp) in build_caches() argument
1245 int ret = build_caches_for_cpu(cpu, caches, &cnt); in build_caches()
1258 struct cpu_cache_level caches[max_caches]; in write_cache() local
1262 ret = build_caches(caches, &cnt); in write_cache()
1266 qsort(&caches, cnt, sizeof(struct cpu_cache_level), cpu_cache_level__sort); in write_cache()
1277 struct cpu_cache_level *c = &caches[i]; in write_cache()
1303 cpu_cache_level__free(&caches[i]); in write_cache()
[all …]

1234567