Home
last modified time | relevance | path

Searched refs:cacheable (Results 1 – 15 of 15) sorted by relevance

/linux/Documentation/userspace-api/
H A Ddma-buf-heaps.rst17 - The ``system`` heap allocates virtually contiguous, cacheable, buffers.
20 cacheable, buffers. Only present if a CMA region is present. Such a
/linux/Documentation/core-api/
H A Ddma-attributes.rst139 functions, it may not be cacheable, and access using CPU load/store
142 Usually this will be used to describe MMIO addresses, or other non-cacheable
150 provided must never be mapped cacheable into the CPU.
/linux/Documentation/arch/x86/
H A Damd-memory-encryption.rst202 Bits[9:0] number of cacheable RMP segment definitions
203 Bit[10] indicates if the number of cacheable RMP segments
237 of cacheable RMP segments (CPUID 0x80000025_EBX[9:0]) if the number of cacheable
/linux/arch/arm/mm/
H A Dproc-arm946.S361 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
362 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
H A Dproc-arm740.S109 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
H A Dproc-arm940.S317 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
H A DKconfig1023 PL310 treats a cacheable write transaction during a Clean &
1045 not automatically drain. This can cause normal, non-cacheable
1099 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
/linux/arch/sparc/mm/
H A Dviking.S96 mov 0x10, %g2 ! set cacheable bit
/linux/drivers/infiniband/hw/mlx5/
H A Dmr.c771 mr->mmkey.cacheable = true; in _mlx5_mr_cache_alloc()
1178 mr->mmkey.cacheable = true; in alloc_cacheable_mr()
2139 if (mr->mmkey.cacheable && !mlx5_umr_revoke_mr_with_lock(mr) && in mlx5r_handle_mkey_cleanup()
H A Dmlx5_ib.h662 u8 cacheable : 1; member
/linux/Documentation/admin-guide/cifs/
H A Dusage.rst656 check to see whether a file is cacheable. CIFS has no way
658 is cacheable (oplocked). Unfortunately, even if a file
659 is not oplocked, it could still be cacheable (ie cifs client
/linux/Documentation/arch/arm64/
H A Dbooting.rst54 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
/linux/Documentation/admin-guide/hw-vuln/
H A Dl1tf.rst81 marked present, never point to cacheable physical memory space.
/linux/arch/arm64/
H A DKconfig765 address for a cacheable mapping of a location is being
816 non-cacheable memory attributes. The workaround depends on a firmware
/linux/Documentation/virt/kvm/
H A Dapi.rst8875 can be safely mapped as cacheable. This relies on the presence of