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Searched refs:bw (Results 1 – 25 of 423) sorted by relevance

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/linux/drivers/net/wireless/broadcom/brcm80211/brcmutil/
H A Dd11.c28 static u16 d11n_bw(enum brcmu_chan_bw bw) in d11n_bw() argument
30 switch (bw) { in d11n_bw()
43 if (ch->bw == BRCMU_CHAN_BW_20) in brcmu_d11n_encchspec()
52 0, d11n_bw(ch->bw)); in brcmu_d11n_encchspec()
60 static u16 d11ac_bw(enum brcmu_chan_bw bw) in d11ac_bw() argument
62 switch (bw) { in d11ac_bw()
79 if (ch->bw == BRCMU_CHAN_BW_20 || ch->sb == BRCMU_CHAN_SB_NONE) in brcmu_d11ac_encchspec()
87 0, d11ac_bw(ch->bw)); in brcmu_d11ac_encchspec()
105 ch->bw = BRCMU_CHAN_BW_20; in brcmu_d11n_decchspec()
109 ch->bw = BRCMU_CHAN_BW_40; in brcmu_d11n_decchspec()
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/linux/drivers/net/wireless/intel/iwlwifi/mld/
H A Dtlc.c264 enum IWL_TLC_MCS_PER_BW bw, in iwl_mld_set_eht_mcs() argument
268 ht_rates[IWL_TLC_NSS_2][bw] |= cpu_to_le32(mcs_msk); in iwl_mld_set_eht_mcs()
271 ht_rates[IWL_TLC_NSS_1][bw] |= cpu_to_le32(mcs_msk); in iwl_mld_set_eht_mcs()
276 iwl_mld_get_eht_mcs_of_bw(enum IWL_TLC_MCS_PER_BW bw, in iwl_mld_get_eht_mcs_of_bw() argument
279 switch (bw) { in iwl_mld_get_eht_mcs_of_bw()
281 return &eht_mcs->bw._80; in iwl_mld_get_eht_mcs_of_bw()
283 return &eht_mcs->bw._160; in iwl_mld_get_eht_mcs_of_bw()
285 return &eht_mcs->bw._320; in iwl_mld_get_eht_mcs_of_bw()
319 enum IWL_TLC_MCS_PER_BW bw; in iwl_mld_fill_eht_rates() local
330 eht_rx_mcs->bw._80.rx_tx_mcs9_max_nss; in iwl_mld_fill_eht_rates()
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/linux/net/ipv4/
H A Dtcp_bbr.c93 struct minmax bw; /* Max recent delivery rate in pkts/uS << 24 */ member
219 return minmax_get(&bbr->bw); in bbr_max_bw()
256 static unsigned long bbr_bw_to_pacing_rate(struct sock *sk, u32 bw, int gain) in bbr_bw_to_pacing_rate() argument
258 u64 rate = bw; in bbr_bw_to_pacing_rate()
270 u64 bw; in bbr_init_pacing_rate_from_rtt() local
279 bw = (u64)tcp_snd_cwnd(tp) * BW_UNIT; in bbr_init_pacing_rate_from_rtt()
280 do_div(bw, rtt_us); in bbr_init_pacing_rate_from_rtt()
282 bbr_bw_to_pacing_rate(sk, bw, bbr_high_gain)); in bbr_init_pacing_rate_from_rtt()
286 static void bbr_set_pacing_rate(struct sock *sk, u32 bw, int gain) in bbr_set_pacing_rate() argument
290 unsigned long rate = bbr_bw_to_pacing_rate(sk, bw, gain); in bbr_set_pacing_rate()
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/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drs-fw.c257 enum IWL_TLC_MCS_PER_BW bw, in rs_fw_set_eht_mcs_nss() argument
261 ht_rates[IWL_TLC_NSS_2][bw] |= cpu_to_le16(mcs_msk); in rs_fw_set_eht_mcs_nss()
264 ht_rates[IWL_TLC_NSS_1][bw] |= cpu_to_le16(mcs_msk); in rs_fw_set_eht_mcs_nss()
269 rs_fw_rs_mcs2eht_mcs(enum IWL_TLC_MCS_PER_BW bw, in rs_fw_rs_mcs2eht_mcs() argument
272 switch (bw) { in rs_fw_rs_mcs2eht_mcs()
274 return &eht_mcs->bw._80; in rs_fw_rs_mcs2eht_mcs()
276 return &eht_mcs->bw._160; in rs_fw_rs_mcs2eht_mcs()
278 return &eht_mcs->bw._320; in rs_fw_rs_mcs2eht_mcs()
298 enum IWL_TLC_MCS_PER_BW bw; in rs_fw_eht_set_enabled_rates() local
308 mcs_rx_20.rx_tx_mcs7_max_nss = eht_rx_mcs->bw._80.rx_tx_mcs9_max_nss; in rs_fw_eht_set_enabled_rates()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_debug.c191 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
192 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
193 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
194 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
195 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
196 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
199 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
200 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
201 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
202 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_utils.c184 context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz; in dml2_copy_clocks_to_dc_state()
185 context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz; in dml2_copy_clocks_to_dc_state()
186 context->bw_ctx.bw.dcn.clk.dramclk_khz = out_clks->uclk_mts / 16; in dml2_copy_clocks_to_dc_state()
187 context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz; in dml2_copy_clocks_to_dc_state()
188 context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz; in dml2_copy_clocks_to_dc_state()
189 context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz; in dml2_copy_clocks_to_dc_state()
190 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz; in dml2_copy_clocks_to_dc_state()
191 context->bw_ctx.bw.dcn.clk.p_state_change_support = out_clks->p_state_supported; in dml2_copy_clocks_to_dc_state()
285 …context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCL… in dml2_calculate_rq_and_dlg_params()
286 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml2_calculate_rq_and_dlg_params()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c295 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
318 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn30_fpu_calculate_wm_and_dlg()
329 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = in dcn30_fpu_calculate_wm_and_dlg()
332 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
370 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
371 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn30_fpu_calculate_wm_and_dlg()
372 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
373 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn30_fpu_calculate_wm_and_dlg()
374 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_fpu_calculate_wm_and_dlg()
375 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_bw.c167 unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points; in icl_qgv_points_mask()
168 unsigned int num_qgv_points = display->bw.max[0].num_qgv_points; in icl_qgv_points_mask()
473 int num_groups = ARRAY_SIZE(display->bw.max); in icl_get_bw_info()
489 struct intel_bw_info *bi = &display->bw.max[i]; in icl_get_bw_info()
501 int ct, bw; in icl_get_bw_info() local
511 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct); in icl_get_bw_info()
514 bw * (100 - sa->derating) / 100); in icl_get_bw_info()
545 int num_groups = ARRAY_SIZE(display->bw.max); in tgl_get_bw_info()
582 struct intel_bw_info *bi = &display->bw.max[i]; in tgl_get_bw_info()
590 bi_next = &display->bw.max[i + 1]; in tgl_get_bw_info()
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/linux/drivers/media/dvb-frontends/
H A Ddib7000m.c316 static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw) in dib7000m_set_bandwidth() argument
320 if (!bw) in dib7000m_set_bandwidth()
321 bw = 8000; in dib7000m_set_bandwidth()
324 state->current_bandwidth = bw; in dib7000m_set_bandwidth()
334 timf = timf * (bw / 50) / 160; in dib7000m_set_bandwidth()
382 … dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw) in dib7000m_reset_pll_common() argument
384 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff)); in dib7000m_reset_pll_common()
385 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff)); in dib7000m_reset_pll_common()
386 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff)); in dib7000m_reset_pll_common()
387 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff)); in dib7000m_reset_pll_common()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_wrapper.c98 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml21_calculate_rq_and_dlg_params()
101 …memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.ar… in dml21_calculate_rq_and_dlg_params()
104 …context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_reg… in dml21_calculate_rq_and_dlg_params()
106 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
107 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
108 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
140 …memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &pln_prog->mcache_allocation, siz… in dml21_calculate_rq_and_dlg_params()
142 memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx], in dml21_calculate_rq_and_dlg_params()
151 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dml21_calculate_rq_and_dlg_params()
152 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dml21_calculate_rq_and_dlg_params()
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H A Ddml21_utils.c177 context->bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
181 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
230 pipe_ctx->plane_res.bw.dppclk_khz = pln_prog->min_clocks.dcn4x.dppclk_khz; in dml21_program_dc_pipe()
231 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz) in dml21_program_dc_pipe()
232 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz; in dml21_program_dc_pipe()
385 …memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * … in dml21_build_fams2_programming()
386 …memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * D… in dml21_build_fams2_programming()
387 …memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_stati… in dml21_build_fams2_programming()
388 …memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)… in dml21_build_fams2_programming()
397 …union dmub_cmd_fams2_config *static_base_state = &context->bw_ctx.bw.dcn.fams2_stream_base_params[… in dml21_build_fams2_programming()
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/linux/drivers/net/wireless/ath/ath11k/
H A Dreg.c502 u16 bw; in ath11k_reg_adjust_bw() local
507 bw = end_freq - start_freq; in ath11k_reg_adjust_bw()
508 bw = min_t(u16, bw, max_bw); in ath11k_reg_adjust_bw()
510 if (bw >= 80 && bw < 160) in ath11k_reg_adjust_bw()
511 bw = 80; in ath11k_reg_adjust_bw()
512 else if (bw >= 40 && bw < 80) in ath11k_reg_adjust_bw()
513 bw = 40; in ath11k_reg_adjust_bw()
514 else if (bw >= 20 && bw < 40) in ath11k_reg_adjust_bw()
515 bw = 20; in ath11k_reg_adjust_bw()
517 bw = 0; in ath11k_reg_adjust_bw()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c502 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 in dcn31_calculate_wm_and_dlg_fp()
523 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
524 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn31_calculate_wm_and_dlg_fp()
525 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn31_calculate_wm_and_dlg_fp()
526 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn31_calculate_wm_and_dlg_fp()
527 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus… in dcn31_calculate_wm_and_dlg_fp()
528 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&cont… in dcn31_calculate_wm_and_dlg_fp()
529 …context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn31_calculate_wm_and_dlg_fp()
530 …context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn31_calculate_wm_and_dlg_fp()
531 …context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&… in dcn31_calculate_wm_and_dlg_fp()
[all …]
/linux/drivers/media/usb/dvb-usb-v2/
H A Dmxl111sf-tuner.c79 u8 bw) in mxl111sf_calc_phy_tune_regs() argument
84 switch (bw) { in mxl111sf_calc_phy_tune_regs()
186 static int mxl1x1sf_tune_rf(struct dvb_frontend *fe, u32 freq, u8 bw) in mxl1x1sf_tune_rf() argument
193 mxl_dbg("(freq = %d, bw = 0x%x)", freq, bw); in mxl1x1sf_tune_rf()
206 reg_ctrl_array = mxl111sf_calc_phy_tune_regs(freq, bw); in mxl1x1sf_tune_rf()
268 u8 bw; in mxl111sf_tuner_set_params() local
275 bw = 0; /* ATSC */ in mxl111sf_tuner_set_params()
278 bw = 1; /* US CABLE */ in mxl111sf_tuner_set_params()
283 bw = 6; in mxl111sf_tuner_set_params()
286 bw = 7; in mxl111sf_tuner_set_params()
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/linux/drivers/net/wireless/ath/ath12k/
H A Dreg.c511 u16 bw; in ath12k_reg_adjust_bw() local
513 bw = end_freq - start_freq; in ath12k_reg_adjust_bw()
514 bw = min_t(u16, bw, max_bw); in ath12k_reg_adjust_bw()
516 if (bw >= 80 && bw < 160) in ath12k_reg_adjust_bw()
517 bw = 80; in ath12k_reg_adjust_bw()
518 else if (bw >= 40 && bw < 80) in ath12k_reg_adjust_bw()
519 bw = 40; in ath12k_reg_adjust_bw()
520 else if (bw < 40) in ath12k_reg_adjust_bw()
521 bw = 20; in ath12k_reg_adjust_bw()
523 return bw; in ath12k_reg_adjust_bw()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c903 &context->bw_ctx.bw.dce)) in dce112_validate_bandwidth()
911 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce112_validate_bandwidth()
912 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce112_validate_bandwidth()
926 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, in dce112_validate_bandwidth()
927 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, in dce112_validate_bandwidth()
928 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce112_validate_bandwidth()
929 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce112_validate_bandwidth()
930 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, in dce112_validate_bandwidth()
931 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, in dce112_validate_bandwidth()
932 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, in dce112_validate_bandwidth()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c206 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
208 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
210 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
212 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
214 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
228 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
234 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
247 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
261 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
276 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
/linux/drivers/net/wireless/realtek/rtw88/
H A Dphy.c1614 u8 bw, u8 rs, u8 ch, s8 pwr_limit) in rtw_phy_set_tx_power_limit() argument
1625 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX || in rtw_phy_set_tx_power_limit()
1629 regd, band, bw, rs, ch_idx, pwr_limit); in rtw_phy_set_tx_power_limit()
1634 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit; in rtw_phy_set_tx_power_limit()
1635 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx]; in rtw_phy_set_tx_power_limit()
1637 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww; in rtw_phy_set_tx_power_limit()
1639 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit; in rtw_phy_set_tx_power_limit()
1640 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx]; in rtw_phy_set_tx_power_limit()
1642 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww; in rtw_phy_set_tx_power_limit()
1649 u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht) in rtw_xref_5g_txpwr_lmt() argument
[all …]
H A Drtw8814a.c113 efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) | in rtw8814a_init_hwcap()
125 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, in rtw8814a_init_hwcap()
549 static void rtw8814a_set_bw_reg_adc(struct rtw_dev *rtwdev, u8 bw) in rtw8814a_set_bw_reg_adc() argument
553 if (bw == RTW_CHANNEL_WIDTH_20) in rtw8814a_set_bw_reg_adc()
555 else if (bw == RTW_CHANNEL_WIDTH_40) in rtw8814a_set_bw_reg_adc()
557 else if (bw == RTW_CHANNEL_WIDTH_80) in rtw8814a_set_bw_reg_adc()
563 static void rtw8814a_set_bw_reg_agc(struct rtw_dev *rtwdev, u8 new_band, u8 bw) in rtw8814a_set_bw_reg_agc() argument
567 if (bw == RTW_CHANNEL_WIDTH_20) { in rtw8814a_set_bw_reg_agc()
569 } else if (bw == RTW_CHANNEL_WIDTH_40) { in rtw8814a_set_bw_reg_agc()
574 } else if (bw == RTW_CHANNEL_WIDTH_80) { in rtw8814a_set_bw_reg_agc()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c566 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
568 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
570 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
572 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
573 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
580 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
582 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
584 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
586 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
587 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c980 &context->bw_ctx.bw.dce)) in dce110_validate_bandwidth()
990 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce110_validate_bandwidth()
991 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce110_validate_bandwidth()
1005 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1006 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1007 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1008 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1009 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1010 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1011 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, in dce110_validate_bandwidth()
[all …]
/linux/net/wireless/
H A Dutil.c1297 bitrate = (rate->bw == RATE_INFO_BW_40) ? 13500000 : 6500000; in cfg80211_calculate_bitrate_ht()
1478 switch (rate->bw) { in cfg80211_calculate_bitrate_vht()
1506 rate->bw, rate->mcs, rate->nss); in cfg80211_calculate_bitrate_vht()
1550 if (rate->bw == RATE_INFO_BW_160 || in cfg80211_calculate_bitrate_he()
1551 (rate->bw == RATE_INFO_BW_HE_RU && in cfg80211_calculate_bitrate_he()
1554 else if (rate->bw == RATE_INFO_BW_80 || in cfg80211_calculate_bitrate_he()
1555 (rate->bw == RATE_INFO_BW_HE_RU && in cfg80211_calculate_bitrate_he()
1558 else if (rate->bw == RATE_INFO_BW_40 || in cfg80211_calculate_bitrate_he()
1559 (rate->bw == RATE_INFO_BW_HE_RU && in cfg80211_calculate_bitrate_he()
1562 else if (rate->bw == RATE_INFO_BW_20 || in cfg80211_calculate_bitrate_he()
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/fw/
H A Drs.c85 const char *iwl_rs_pretty_bw(int bw) in iwl_rs_pretty_bw() argument
87 if (bw >= ARRAY_SIZE(pretty_bw)) in iwl_rs_pretty_bw()
90 return pretty_bw[bw]; in iwl_rs_pretty_bw()
99 u32 bw = (rate & RATE_MCS_CHAN_WIDTH_MSK) >> in rs_pretty_print_rate() local
141 rate, type, iwl_rs_pretty_ant(ant), iwl_rs_pretty_bw(bw), mcs, nss, in rs_pretty_print_rate()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1153 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1154 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1155 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1156 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1158 if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) in dcn20_calculate_dlg_params()
1159 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; in dcn20_calculate_dlg_params()
1161 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()
1162 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn20_calculate_dlg_params()
1163 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn20_calculate_dlg_params()
1170 …context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_swit… in dcn20_calculate_dlg_params()
[all …]
/linux/include/net/
H A Dregulatory.h225 #define REG_RULE_EXT(start, end, bw, gain, eirp, dfs_cac, reg_flags) \ argument
229 .freq_range.max_bandwidth_khz = MHZ_TO_KHZ(bw), \
236 #define REG_RULE(start, end, bw, gain, eirp, reg_flags) \ argument
237 REG_RULE_EXT(start, end, bw, gain, eirp, 0, reg_flags)

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