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Searched refs:bit_off (Results 1 – 25 of 50) sorted by relevance

12

/linux/drivers/pinctrl/
H A Dpinctrl-digicolor.c130 int bit_off, reg_off; in dc_set_mux() local
133 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
136 reg &= ~(3 << bit_off); in dc_set_mux()
137 reg |= (selector << bit_off); in dc_set_mux()
148 int bit_off, reg_off; in dc_pmx_request_gpio() local
151 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
154 if ((reg & (3 << bit_off)) != 0) in dc_pmx_request_gpio()
172 int bit_off = gpio % PINS_PER_COLLECTION; in dc_gpio_direction_input() local
178 drive &= ~BIT(bit_off); in dc_gpio_direction_input()
192 int bit_off = gpio % PINS_PER_COLLECTION; in dc_gpio_direction_output() local
[all …]
/linux/mm/
H A Dpercpu.c320 int bit_off = ALIGN(block->contig_hint_start, align) - in pcpu_check_block_hint() local
323 return bit_off + bits <= block->contig_hint; in pcpu_check_block_hint()
365 static void pcpu_next_md_free_region(struct pcpu_chunk *chunk, int *bit_off, in pcpu_next_md_free_region() argument
368 int i = pcpu_off_to_block_index(*bit_off); in pcpu_next_md_free_region()
369 int block_off = pcpu_off_to_block_off(*bit_off); in pcpu_next_md_free_region()
394 *bit_off = pcpu_block_off_to_off(i, in pcpu_next_md_free_region()
402 *bit_off = (i + 1) * PCPU_BITMAP_BLOCK_BITS - block->right_free; in pcpu_next_md_free_region()
421 int align, int *bit_off, int *bits) in pcpu_next_fit_region() argument
423 int i = pcpu_off_to_block_index(*bit_off); in pcpu_next_fit_region()
424 int block_off = pcpu_off_to_block_off(*bit_off); in pcpu_next_fit_region()
[all …]
/linux/drivers/pinctrl/sunplus/
H A Dsppctl.c114 u32 bit_off; in sppctl_get_reg_and_bit_offset() local
118 bit_off = offset % 32; in sppctl_get_reg_and_bit_offset()
120 return bit_off; in sppctl_get_reg_and_bit_offset()
125 u32 bit_off; in sppctl_get_moon_reg_and_bit_offset() local
134 bit_off = offset % 16; in sppctl_get_moon_reg_and_bit_offset()
136 return bit_off; in sppctl_get_moon_reg_and_bit_offset()
141 u32 bit_off; in sppctl_prep_moon_reg_and_offset() local
143 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); in sppctl_prep_moon_reg_and_offset()
145 return SPPCTL_SET_MOON_REG_BIT(bit_off); in sppctl_prep_moon_reg_and_offset()
147 return SPPCTL_CLR_MOON_REG_BIT(bit_off); in sppctl_prep_moon_reg_and_offset()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_vbif.c62 u32 bit_off; in dpu_hw_set_mem_type() local
80 bit_off = (xin_id & 0x7) * 4; in dpu_hw_set_mem_type()
82 reg_val &= ~(0x7 << bit_off); in dpu_hw_set_mem_type()
83 reg_val |= (value & 0x7) << bit_off; in dpu_hw_set_mem_type()
93 u32 bit_off; in dpu_hw_set_limit_conf() local
101 bit_off = (xin_id % 4) * 8; in dpu_hw_set_limit_conf()
103 reg_val &= ~(0xFF << bit_off); in dpu_hw_set_limit_conf()
104 reg_val |= (limit) << bit_off; in dpu_hw_set_limit_conf()
114 u32 bit_off; in dpu_hw_get_limit_conf() local
123 bit_off = (xin_id % 4) * 8; in dpu_hw_get_limit_conf()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_1_7_msm8996.h26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
31 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
32 [DPU_CLK_CTRL_RGB2] = { .reg_off = 0x2bc, .bit_off = 4 },
33 [DPU_CLK_CTRL_RGB3] = { .reg_off = 0x2c4, .bit_off = 4 },
34 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
[all …]
H A Ddpu_6_0_sm8250.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_7_0_sm8350.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_8_1_sm8450.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_5_0_sm8150.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
35 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_8_4_sa8775p.h24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
32 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_4_0_sdm845.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
H A Ddpu_4_1_sdm670.h15 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
16 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
17 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
18 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
19 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
H A Ddpu_6_4_sm6350.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
29 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_5_1_sc8180x.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
35 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_8_0_sc8280xp.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_1_15_msm8917.h23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
25 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
H A Ddpu_5_3_sm6150.h24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
29 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_1_14_msm8937.h23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
25 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
H A Ddpu_6_2_sc7180.h23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
27 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_1_16_msm8953.h23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
25 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
H A Ddpu_5_2_sm7150.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_5_4_sm6125.h26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
29 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
H A Ddefiner.c54 #define _HWS_SET32(p, v, byte_off, bit_off, mask) \ argument
60 (~((mask) << (bit_off)))) | \
62 (bit_off))); \
66 #define HWS_SET32(p, v, byte_off, bit_off, mask) \ argument
68 if (unlikely((bit_off) < 0)) { \
69 u32 _bit_off = -1 * (bit_off); \
73 (bit_off + BITS_IN_DW) % BITS_IN_DW, second_dw_mask); \
75 _HWS_SET32(p, v, byte_off, (bit_off), (mask)); \
80 #define HWS_GET32(p, byte_off, bit_off, mask) \ argument
81 ((be32_to_cpu(*((__be32 *)(p) + ((byte_off) / 4))) >> (bit_off)) & (mask))
[all …]
/linux/fs/ocfs2/
H A Dlocalalloc.h39 u32 *bit_off,
45 u32 bit_off,
H A Dlocalalloc.c718 u32 *bit_off, in ocfs2_claim_local_alloc_bits() argument
743 *bit_off = le32_to_cpu(la->la_bm_off) + start; in ocfs2_claim_local_alloc_bits()
773 u32 bit_off, in ocfs2_free_local_alloc_bits() argument
790 start = bit_off - le32_to_cpu(la->la_bm_off); in ocfs2_free_local_alloc_bits()
947 int bit_off, left, count, start; in ocfs2_sync_local_to_main() local
973 bit_off = ocfs2_find_next_zero_bit(bitmap, left, start); in ocfs2_sync_local_to_main()
974 if ((bit_off < left) && (bit_off == start)) { in ocfs2_sync_local_to_main()
999 if (bit_off >= left) in ocfs2_sync_local_to_main()
1002 start = bit_off + 1; in ocfs2_sync_local_to_main()

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