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Searched refs:bankw (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Devergreen_cs.c178 unsigned bankw; member
270 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; in evergreen_surface_check_2d()
349 switch (surf->bankw) { in evergreen_surface_value_conv_check()
350 case 0: surf->bankw = 1; break; in evergreen_surface_value_conv_check()
351 case 1: surf->bankw = 2; break; in evergreen_surface_value_conv_check()
352 case 2: surf->bankw = 4; break; in evergreen_surface_value_conv_check()
353 case 3: surf->bankw = 8; break; in evergreen_surface_value_conv_check()
356 __func__, __LINE__, prefix, surf->bankw); in evergreen_surface_value_conv_check()
412 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
488 surf.bankw, surf.bankh, in evergreen_cs_track_validate_cb()
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H A Dradeon_object.c611 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local
613 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
618 switch (bankw) { in radeon_bo_set_tiling_flags()
H A Dradeon.h356 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c186 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() local
188 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
200 tiling_info->gfx8.bank_width = bankw; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c1915 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local
1917 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1926 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); in dce_v8_0_crtc_do_set_base()
H A Ddce_v6_0.c2003 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v6_0_crtc_do_set_base() local
2005 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
2014 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); in dce_v6_0_crtc_do_set_base()
H A Ddce_v10_0.c1976 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local
1978 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1989 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); in dce_v10_0_crtc_do_set_base()