Searched refs:asic_blank_end (Results 1 – 6 of 6) sorted by relevance
168 uint32_t asic_blank_end; in optc1_program_timing() local205 asic_blank_end = asic_blank_start - in optc1_program_timing()212 OTG_H_BLANK_END, asic_blank_end); in optc1_program_timing()243 asic_blank_end = asic_blank_start - in optc1_program_timing()250 OTG_V_BLANK_END, asic_blank_end); in optc1_program_timing()349 uint32_t asic_blank_end; in optc1_set_vtg_params() local363 asic_blank_end = v_init - in optc1_set_vtg_params()369 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; in optc1_set_vtg_params()377 if ((optc1->vstartup_start/2)*2 > asic_blank_end) in optc1_set_vtg_params()
762 int vesa_sync_start, asic_blank_end, asic_blank_start; in dcn_validate_bandwidth() local1220 asic_blank_end = (pipe->stream->timing.v_total - in dcn_validate_bandwidth()1225 asic_blank_start = asic_blank_end + in dcn_validate_bandwidth()1232 pipe->pipe_dlg_param.vblank_end = asic_blank_end; in dcn_validate_bandwidth()
1110 uint32_t asic_blank_end = 0; in dcn20_adjust_freesync_v_startup() local1129 asic_blank_end = asic_blank_start - in dcn20_adjust_freesync_v_startup()1135 newVstartup = asic_blank_end + 1; in dcn20_adjust_freesync_v_startup()
4817 uint32_t asic_blank_end = 0; in adaptive_sync_override_dp_info_packets_sdp_line_num() local4826 asic_blank_end = (asic_blank_start - tg->v_border_bottom - in adaptive_sync_override_dp_info_packets_sdp_line_num()4829 if (vstartup_start > asic_blank_end) { in adaptive_sync_override_dp_info_packets_sdp_line_num()4830 v_update = (tg->v_total - (vstartup_start - asic_blank_end)); in adaptive_sync_override_dp_info_packets_sdp_line_num()
3930 int asic_blank_end; in dcn10_get_vupdate_offset_from_vsync() local3942 asic_blank_end = (patched_crtc_timing.v_total - in dcn10_get_vupdate_offset_from_vsync()3947 return asic_blank_end - in dcn10_get_vupdate_offset_from_vsync()
1616 uint32_t asic_blank_end = 0; in dcn20_adjust_freesync_v_startup() local1635 asic_blank_end = asic_blank_start - in dcn20_adjust_freesync_v_startup()1640 newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start); in dcn20_adjust_freesync_v_startup()