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/linux/include/linux/soc/pxa/
H A Dcpu.h61 unsigned int _id = (id) & 0xf3f0; \
62 _id == 0x2120; \
67 unsigned int _id = (id) & 0xf3ff; \
68 _id <= 0x2105; \
73 unsigned int _id = (id) & 0xffff; \
74 _id == 0x2d06; \
79 unsigned int _id = (id) & 0xf300; \
80 _id == 0x2100; \
92 unsigned int _id = (id) >> 4 & 0xfff; \
93 _id == 0x411; \
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/linux/drivers/clk/renesas/
H A Drzg2l-cpg.h149 #define DEF_TYPE(_name, _id, _type...) \ argument
150 { .name = _name, .id = _id, .type = _type }
151 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
152 DEF_TYPE(_name, _id, _type, .parent = _parent)
153 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
154 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
155 #define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \ argument
156 DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \
158 #define DEF_INPUT(_name, _id) \ argument
159 DEF_TYPE(_name, _id, CLK_TYPE_IN)
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H A Drcar-gen4-cpg.h35 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
36 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
38 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
39 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
41 #define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ argument
42 DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
46 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \ argument
47 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
49 #define DEF_GEN4_PLL_F8_25(_name, _idx, _id, _parent) \ argument
50 DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F8_25, _parent, .offset = _idx)
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H A Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
38 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
41 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
43 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ argument
44 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
48 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ argument
50 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
53 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
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H A Drenesas-cpg-mssr.h71 #define DEF_TYPE(_name, _id, _type...) \ argument
72 { .name = _name, .id = _id, .type = _type }
73 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
74 DEF_TYPE(_name, _id, _type, .parent = _parent)
76 #define DEF_INPUT(_name, _id) \ argument
77 DEF_TYPE(_name, _id, CLK_TYPE_IN)
78 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
79 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
80 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
81 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
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H A Drzv2h-cpg.h193 #define DEF_TYPE(_name, _id, _type...) \ argument
194 { .name = _name, .id = _id, .type = _type }
195 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
196 DEF_TYPE(_name, _id, _type, .parent = _parent)
197 #define DEF_PLL(_name, _id, _parent, _pll_packed) \ argument
198 DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.pll = _pll_packed)
199 #define DEF_INPUT(_name, _id) \ argument
200 DEF_TYPE(_name, _id, CLK_TYPE_IN)
201 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ argument
202 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
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/linux/arch/powerpc/include/asm/
H A Dperf_event_server.h171 #define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix argument
172 #define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr argument
174 #define EVENT_ATTR(_name, _id, _suffix) \ argument
175 PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), _id, \
178 #define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g) argument
179 #define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g) argument
181 #define CACHE_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _c) argument
182 #define CACHE_EVENT_PTR(_id) EVENT_PTR(_id, _c) argument
184 #define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _p) argument
185 #define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p) argument
/linux/drivers/clk/samsung/
H A Dclk.h45 #define ALIAS(_id, dname, a) \ argument
47 .id = _id, \
70 #define FRATE(_id, cname, pname, f, frate) \ argument
72 .id = _id, \
97 #define FFACTOR(_id, cname, pname, m, d, f) \ argument
99 .id = _id, \
131 #define __MUX(_id, cname, pnames, o, s, w, f, mf) \ argument
133 .id = _id, \
144 #define MUX(_id, cname, pnames, o, s, w) \ argument
145 __MUX(_id, cname, pnames, o, s, w, CLK_SET_RATE_NO_REPARENT, 0)
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/linux/include/linux/
H A Dmod_devicetable.h441 #define BCMA_CORE(_manuf, _id, _rev, _class) \ argument
442 { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
616 #define MDIO_ID_ARGS(_id) \ argument
617 ((_id)>>31) & 1, ((_id)>>30) & 1, ((_id)>>29) & 1, ((_id)>>28) & 1, \
618 ((_id)>>27) & 1, ((_id)>>26) & 1, ((_id)>>25) & 1, ((_id)>>24) & 1, \
619 ((_id)>>23) & 1, ((_id)>>22) & 1, ((_id)>>21) & 1, ((_id)>>20) & 1, \
620 ((_id)>>19) & 1, ((_id)>>18) & 1, ((_id)>>17) & 1, ((_id)>>16) & 1, \
621 ((_id)>>15) & 1, ((_id)>>14) & 1, ((_id)>>13) & 1, ((_id)>>12) & 1, \
622 ((_id)>>11) & 1, ((_id)>>10) & 1, ((_id)>>9) & 1, ((_id)>>8) & 1, \
623 ((_id)>>7) & 1, ((_id)>>6) & 1, ((_id)>>5) & 1, ((_id)>>4) & 1, \
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/linux/drivers/clk/mediatek/
H A Dclk-mtk.h39 #define GATE_DUMMY(_id, _name) { \ argument
40 .id = _id, \
53 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
54 .id = _id, \
74 #define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) { \ argument
75 .id = _id, \
83 #define FACTOR(_id, _name, _parent, _mult, _div) \ argument
84 FACTOR_FLAGS(_id, _name, _parent, _mult, _div, CLK_SET_RATE_PARENT)
114 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
116 .id = _id, \
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H A Dclk-mt8188-infra_ao.c45 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
49 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
50 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
52 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
56 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
57 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
59 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
60 GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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H A Dclk-mux.h47 #define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ argument
51 .id = _id, \
68 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
71 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
76 #define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \ argument
79 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
89 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
92 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
97 #define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \ argument
100 GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \
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H A Dclk-mt8196-venc.c42 #define GATE_VEN10(_id, _name, _parent, _shift) { \ argument
43 .id = _id, \
52 #define GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, _flags) { \ argument
53 .id = _id, \
64 #define GATE_HWV_VEN10(_id, _name, _parent, _shift) \ argument
65 GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, 0)
67 #define GATE_HWV_VEN11(_id, _name, _parent, _shift) { \ argument
68 .id = _id, \
114 #define GATE_VEN20(_id, _name, _parent, _shift) { \ argument
115 .id = _id, \
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H A Dclk-mt8195-infra_ao.c44 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
51 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
52 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
58 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
59 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
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H A Dclk-mt8196-vdec.c54 #define GATE_HWV_VDE20(_id, _name, _parent, _shift) { \ argument
55 .id = _id, \
65 #define GATE_HWV_VDE21(_id, _name, _parent, _shift) { \ argument
66 .id = _id, \
76 #define GATE_HWV_VDE22(_id, _name, _parent, _shift) { \ argument
77 .id = _id, \
155 #define GATE_HWV_VDE10(_id, _name, _parent, _shift) { \ argument
156 .id = _id, \
166 #define GATE_HWV_VDE11(_id, _name, _parent, _shift) { \ argument
167 .id = _id, \
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H A Dclk-mt8188-vdo1.c52 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
55 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
56 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
58 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
59 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
61 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
62 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
64 #define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
65 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_3_cg_regs, _shift, \
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H A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
H A Dclk-mt8186-infra_ao.c38 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
39 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
42 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
43 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
45 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
49 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
50 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
52 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
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H A Dclk-mt8195-vdo1.c43 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
44 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
46 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
47 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
50 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
53 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \
56 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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/linux/drivers/regulator/
H A Dmax77541-regulator.c55 #define MAX77540_BUCK(_id, _ops) \ argument
56 { .id = MAX77541_BUCK ## _id, \
57 .name = "buck"#_id, \
58 .of_match = "buck"#_id, \
61 .enable_mask = MAX77541_BIT_M ## _id ## _EN, \
66 .vsel_reg = MAX77541_REG_M ## _id ## _VOUT, \
68 .vsel_range_reg = MAX77541_REG_M ## _id ## _CFG1, \
74 #define MAX77541_BUCK(_id, _ops) \ argument
75 { .id = MAX77541_BUCK ## _id, \
76 .name = "buck"#_id, \
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H A Dmax77826-regulator.c118 #define MAX77826_LDO(_id, _type) \ argument
119 [MAX77826_LDO ## _id] = { \
120 .id = MAX77826_LDO ## _id, \
121 .name = "LDO"#_id, \
122 .of_match = of_match_ptr("LDO"#_id), \
128 .enable_reg = MAX77826_REG_LDO_OPMD1 + (_id - 1) / 4, \
129 .enable_mask = BIT(((_id - 1) % 4) * 2 + 1), \
130 .vsel_reg = MAX77826_REG_LDO1_CFG + (_id - 1), \
135 #define MAX77826_BUCK(_idx, _id, _ops) \ argument
136 [MAX77826_ ## _id] = { \
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/linux/drivers/clk/pistachio/
H A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
21 .id = _id, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
41 .id = _id, \
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
61 .id = _id, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
71 .id = _id, \
86 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
88 .id = _id, \
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/linux/drivers/clk/rockchip/
H A Dclk.h556 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ argument
559 .id = _id, \
706 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ argument
709 .id = _id, \
727 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \ argument
730 .id = _id, \
749 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ argument
752 .id = _id, \
767 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\ argument
770 .id = _id, \
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/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-audsys-clk.c28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
29 .id = _id, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
49 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
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/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-audsys-clk.c28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
29 .id = _id, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
49 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
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