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Searched refs:__base (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/thermal/mediatek/
H A Dlvts_thermal.c24 #define LVTS_MONCTL0(__base) (__base + 0x0000) argument
25 #define LVTS_MONCTL1(__base) (__base + 0x0004) argument
26 #define LVTS_MONCTL2(__base) (__base + 0x0008) argument
27 #define LVTS_MONINT(__base) (__base + 0x000C) argument
28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) argument
29 #define LVTS_MONIDET0(__base) (__base + 0x0014) argument
30 #define LVTS_MONIDET1(__base) (__base + 0x0018) argument
31 #define LVTS_MONIDET2(__base) (__base + 0x001C) argument
32 #define LVTS_MONIDET3(__base) (__base + 0x0020) argument
33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) argument
[all …]
/linux/drivers/clocksource/
H A Dtimer-nxp-stm.c25 #define STM_CR(__base) (__base) argument
32 #define STM_CNT(__base) ((__base) + 0x04) argument
34 #define STM_CCR0(__base) ((__base) + 0x10) argument
35 #define STM_CCR1(__base) ((__base) + 0x20) argument
36 #define STM_CCR2(__base) ((__base) + 0x30) argument
37 #define STM_CCR3(__base) ((__base) + 0x40) argument
41 #define STM_CIR0(__base) ((__base) + 0x14) argument
42 #define STM_CIR1(__base) ((__base) + 0x24) argument
43 #define STM_CIR2(__base) ((__base) + 0x34) argument
44 #define STM_CIR3(__base) ((__base) + 0x44) argument
[all …]
H A Dtimer-nxp-pit.c21 #define PITMCR(__base) (__base) argument
26 #define PITLDVAL(__base) (__base) argument
27 #define PITTCTRL(__base) ((__base) + 0x08) argument
30 #define PITCVAL(__base) ((__base) + 0x04) argument
35 #define PITTFLG(__base) ((__base) + 0x0c) argument
/linux/include/asm-generic/
H A Ddiv64.h46 uint32_t __base = (base); \
48 __rem = ((uint64_t)(n)) % __base; \
49 (n) = ((uint64_t)(n)) / __base; \
181 uint32_t __base = (base); \
184 if (__builtin_constant_p(__base) && \
185 is_power_of_2(__base)) { \
186 __rem = (n) & (__base - 1); \
187 (n) >>= ilog2(__base); \
188 } else if (__builtin_constant_p(__base) && \
189 __base != 0) { \
[all …]
/linux/drivers/iio/adc/
H A Dnxp-sar-adc.c40 #define NXP_SAR_ADC_CDR(__base, __channel) (((__base) + 0x100) + ((__channel) * 0x4)) argument
46 #define NXP_SAR_ADC_MCR(__base) ((__base) + 0x00) argument
60 #define NXP_SAR_ADC_MSR(__base) ((__base) + 0x04) argument
66 #define NXP_SAR_ADC_ISR(__base) ((__base) + 0x10) argument
71 #define NXP_SAR_ADC_CEOCFR0(__base) ((__base) + 0x14) argument
72 #define NXP_SAR_ADC_CEOCFR1(__base) ((__base) + 0x18) argument
77 #define NXP_SAR_ADC_IMR(__base) ((__base) + 0x20) argument
80 #define NXP_SAR_ADC_CIMR0(__base) ((__base) + 0x24) argument
81 #define NXP_SAR_ADC_CIMR1(__base) ((__base) + 0x28) argument
84 #define NXP_SAR_ADC_DMAE(__base) ((__base) + 0x40) argument
[all …]
/linux/arch/x86/include/asm/
H A Ddiv64.h24 unsigned long __upper, __low, __high, __mod, __base; \
25 __base = (base); \
26 if (__builtin_constant_p(__base) && is_power_of_2(__base)) { \
27 __mod = n & (__base - 1); \
28 n >>= ilog2(__base); \
33 __upper = __high % (__base); \
34 __high = __high / (__base); \
37 : "rm" (__base), "0" (__low), "1" (__upper)); \
/linux/include/net/netfilter/
H A Dnf_tables_offload.h79 #define NFT_OFFLOAD_MATCH_FLAGS(__key, __base, __field, __len, __reg, __flags) \ argument
81 offsetof(struct nft_flow_key, __base); \
83 offsetof(struct nft_flow_key, __base.__field); \
88 #define NFT_OFFLOAD_MATCH(__key, __base, __field, __len, __reg) \ argument
89 NFT_OFFLOAD_MATCH_FLAGS(__key, __base, __field, __len, __reg, 0)
91 #define NFT_OFFLOAD_MATCH_EXACT(__key, __base, __field, __len, __reg) \ argument
92 NFT_OFFLOAD_MATCH(__key, __base, __field, __len, __reg) \
/linux/drivers/watchdog/
H A Ds32g_wdt.c20 #define S32G_SWT_CR(__base) ((__base) + 0x00) /* Control Register offset */ argument
26 #define S32G_SWT_TO(__base) ((__base) + 0x08) /* Timeout Register offset */ argument
28 #define S32G_SWT_SR(__base) ((__base) + 0x10) /* Service Register offset */ argument
32 #define S32G_SWT_CO(__base) ((__base) + 0x14) /* Counter output register */ argument
/linux/arch/powerpc/boot/
H A Dstdio.c33 unsigned int __base = (base); \
35 __rem = ((unsigned long long)(n)) % __base; \
36 (n) = ((unsigned long long)(n)) / __base; \
49 unsigned int __base = (base); \
53 __rem = (unsigned int)(n) % __base; \
54 (n) = (unsigned int)(n) / __base; \
56 __rem = __div64_32(&(n), __base); \
/linux/arch/m68k/include/asm/
H A Ddiv64.h19 unsigned long __base = (base); \
25 : "d" (__base), "0" (__n.n32[0])); \
29 : "d" (__base), "1" (__upper), "0" (__n.n32[1])); \
/linux/arch/arm/include/asm/
H A Ddiv64.h26 register unsigned int __base asm("r4") = base; in __div64_32()
35 : "r" (__base) in __div64_32()
/linux/arch/alpha/boot/
H A Dstdio.c18 unsigned int __base = (base); \
20 __rem = ((unsigned long long)(n)) % __base; \
21 (n) = ((unsigned long long)(n)) / __base; \
/linux/drivers/gpu/drm/vmwgfx/
H A Dttm_object.h285 #define ttm_base_object_kfree(__object, __base)\ argument
286 kfree_rcu(__object, __base.rhead)
/linux/tools/sched_ext/include/scx/
H A Dcommon.bpf.h247 u64 __base = (u64)&(base); \
248 u64 __addr = (u64)&((base) member) - __base; \
257 : "r"(__base), \
280 u64 __base = (u64)arr; \
281 u64 __addr = (u64)&(arr[i]) - __base; \
288 : "r"(__base), \
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed.h945 #define GET_GTT_REG_ADDR(__base, __offset, __idx) \ argument
946 ((__base) + __offset ## _GTT_OFFSET((__idx)))
948 #define GET_GTT_BDQ_REG_ADDR(__base, __offset, __idx, __bdq_idx) \ argument
949 ((__base) + __offset ## _GTT_OFFSET((__idx), (__bdq_idx)))
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dregs.h15 struct __base { struct
21 const struct __base *base; argument
H A Dmmio.c20 static const struct __base mt7996_reg_base[] = {
/linux/drivers/net/ethernet/amd/
H A Dsunlance.c277 do { void __iomem *__base = (__lp)->lregs; \
278 sbus_writew(LE_CSR0, __base + RAP); \
279 sbus_writew(LE_C0_STOP, __base + RDP); \
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00queue.c1113 #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ in rt2x00queue_alloc_entries() argument
1114 (((char *)(__base)) + ((__limit) * (__esize)) + \ in rt2x00queue_alloc_entries()