Searched refs:WRITE_DATA_DST_SEL (Results 1 – 12 of 12) sorted by relevance
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
266 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
130 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
378 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
107 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
520 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()636 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()6018 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()6027 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()6123 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v11_0_ring_emit_gfx_shadow()6234 WRITE_DATA_DST_SEL(8) | in gfx_v11_0_ring_emit_de_meta()
4005 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()4098 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()8782 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8791 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8918 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_ce_meta()8954 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_de_meta()
525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_0_ring_test_ib()4528 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()4537 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3742 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5684 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5698 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5705 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5716 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5727 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5062 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5077 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5085 WRITE_DATA_DST_SEL(0))); in si_vm_flush()