1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2021 Maxlinear Corporation
3 * Copyright (C) 2020 Intel Corporation
4 *
5 * Drivers for Maxlinear Ethernet GPY
6 *
7 */
8
9 #include <linux/module.h>
10 #include <linux/bitfield.h>
11 #include <linux/hwmon.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/polynomial.h>
15 #include <linux/property.h>
16 #include <linux/netdevice.h>
17
18 /* PHY ID */
19 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC
20 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9
21 #define PHY_ID_GPY2xx 0x67C9DC00
22 #define PHY_ID_GPY115B 0x67C9DF00
23 #define PHY_ID_GPY115C 0x67C9DF10
24 #define PHY_ID_GPY211B 0x67C9DE08
25 #define PHY_ID_GPY211C 0x67C9DE10
26 #define PHY_ID_GPY212B 0x67C9DE09
27 #define PHY_ID_GPY212C 0x67C9DE20
28 #define PHY_ID_GPY215B 0x67C9DF04
29 #define PHY_ID_GPY215C 0x67C9DF20
30 #define PHY_ID_GPY241B 0x67C9DE40
31 #define PHY_ID_GPY241BM 0x67C9DE80
32 #define PHY_ID_GPY245B 0x67C9DEC0
33 #define PHY_ID_MXL86211C 0xC1335400
34 #define PHY_ID_MXL86252 0xC1335520
35 #define PHY_ID_MXL86282 0xC1335500
36
37 #define PHY_CTL1 0x13
38 #define PHY_CTL1_MDICD BIT(3)
39 #define PHY_CTL1_MDIAB BIT(2)
40 #define PHY_CTL1_AMDIX BIT(0)
41 #define PHY_MIISTAT 0x18 /* MII state */
42 #define PHY_IMASK 0x19 /* interrupt mask */
43 #define PHY_ISTAT 0x1A /* interrupt status */
44 #define PHY_LED 0x1B /* LEDs */
45 #define PHY_FWV 0x1E /* firmware version */
46
47 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)
48 #define PHY_MIISTAT_DPX BIT(3)
49 #define PHY_MIISTAT_LS BIT(10)
50
51 #define PHY_MIISTAT_SPD_10 0
52 #define PHY_MIISTAT_SPD_100 1
53 #define PHY_MIISTAT_SPD_1000 2
54 #define PHY_MIISTAT_SPD_2500 4
55
56 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
57 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
58 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
59 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */
60 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */
61 #define PHY_IMASK_LSTC BIT(0) /* Link state change */
62 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \
63 PHY_IMASK_LSPC | \
64 PHY_IMASK_DXMC | \
65 PHY_IMASK_ADSC | \
66 PHY_IMASK_ANC)
67
68 #define GPY_MAX_LEDS 4
69 #define PHY_LED_POLARITY(idx) BIT(12 + (idx))
70 #define PHY_LED_HWCONTROL(idx) BIT(8 + (idx))
71 #define PHY_LED_ON(idx) BIT(idx)
72
73 #define PHY_FWV_REL_MASK BIT(15)
74 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8)
75 #define PHY_FWV_MINOR_MASK GENMASK(7, 0)
76
77 #define PHY_PMA_MGBT_POLARITY 0x82
78 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0)
79 #define PHY_MDI_MDI_X_NORMAL 0x3
80 #define PHY_MDI_MDI_X_AB 0x2
81 #define PHY_MDI_MDI_X_CD 0x1
82 #define PHY_MDI_MDI_X_CROSS 0x0
83
84 /* LED */
85 #define VSPEC1_LED(idx) (1 + (idx))
86 #define VSPEC1_LED_BLINKS GENMASK(15, 12)
87 #define VSPEC1_LED_PULSE GENMASK(11, 8)
88 #define VSPEC1_LED_CON GENMASK(7, 4)
89 #define VSPEC1_LED_BLINKF GENMASK(3, 0)
90
91 #define VSPEC1_LED_LINK10 BIT(0)
92 #define VSPEC1_LED_LINK100 BIT(1)
93 #define VSPEC1_LED_LINK1000 BIT(2)
94 #define VSPEC1_LED_LINK2500 BIT(3)
95
96 #define VSPEC1_LED_TXACT BIT(0)
97 #define VSPEC1_LED_RXACT BIT(1)
98 #define VSPEC1_LED_COL BIT(2)
99 #define VSPEC1_LED_NO_CON BIT(3)
100
101 /* SGMII */
102 #define VSPEC1_SGMII_CTRL 0x08
103 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */
104 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */
105 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \
106 VSPEC1_SGMII_CTRL_ANRS)
107
108 /* Temperature sensor */
109 #define VSPEC1_TEMP_STA 0x0E
110 #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0)
111
112 /* Mailbox */
113 #define VSPEC1_MBOX_DATA 0x5
114 #define VSPEC1_MBOX_ADDRLO 0x6
115 #define VSPEC1_MBOX_CMD 0x7
116 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0)
117 #define VSPEC1_MBOX_CMD_RD (0 << 8)
118 #define VSPEC1_MBOX_CMD_READY BIT(15)
119
120 /* WoL */
121 #define VPSPEC2_WOL_CTL 0x0E06
122 #define VPSPEC2_WOL_AD01 0x0E08
123 #define VPSPEC2_WOL_AD23 0x0E09
124 #define VPSPEC2_WOL_AD45 0x0E0A
125 #define WOL_EN BIT(0)
126
127 /* Internal registers, access via mbox */
128 #define REG_GPIO0_OUT 0xd3ce00
129
130 struct gpy_priv {
131 /* serialize mailbox acesses */
132 struct mutex mbox_lock;
133
134 u8 fw_major;
135 u8 fw_minor;
136 u32 wolopts;
137
138 /* It takes 3 seconds to fully switch out of loopback mode before
139 * it can safely re-enter loopback mode. Record the time when
140 * loopback is disabled. Check and wait if necessary before loopback
141 * is enabled.
142 */
143 u64 lb_dis_to;
144 };
145
146 static const struct {
147 int major;
148 int minor;
149 } ver_need_sgmii_reaneg[] = {
150 {7, 0x6D},
151 {8, 0x6D},
152 {9, 0x73},
153 };
154
155 #if IS_ENABLED(CONFIG_HWMON)
156 /* The original translation formulae of the temperature (in degrees of Celsius)
157 * are as follows:
158 *
159 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
160 * 3.0762e-1*(N^1) + -5.2156e1
161 *
162 * where [-52.156, 137.961]C and N = [0, 1023].
163 *
164 * They must be accordingly altered to be suitable for the integer arithmetics.
165 * The technique is called 'factor redistribution', which just makes sure the
166 * multiplications and divisions are made so to have a result of the operations
167 * within the integer numbers limit. In addition we need to translate the
168 * formulae to accept millidegrees of Celsius. Here what it looks like after
169 * the alterations:
170 *
171 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) +
172 * 307620e-3*(N^1) + -52156
173 *
174 * where T = [-52156, 137961]mC and N = [0, 1023].
175 */
176 static const struct polynomial poly_N_to_temp = {
177 .terms = {
178 {4, -25761, 1000, 1},
179 {3, 97332, 1000, 1},
180 {2, -191650, 1000, 1},
181 {1, 307620, 1000, 1},
182 {0, -52156, 1, 1}
183 }
184 };
185
gpy_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)186 static int gpy_hwmon_read(struct device *dev,
187 enum hwmon_sensor_types type,
188 u32 attr, int channel, long *value)
189 {
190 struct phy_device *phydev = dev_get_drvdata(dev);
191 int ret;
192
193 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
194 if (ret < 0)
195 return ret;
196 if (!ret)
197 return -ENODATA;
198
199 *value = polynomial_calc(&poly_N_to_temp,
200 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret));
201
202 return 0;
203 }
204
mxl862x2_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)205 static int mxl862x2_hwmon_read(struct device *dev,
206 enum hwmon_sensor_types type,
207 u32 attr, int channel, long *value)
208 {
209 struct phy_device *phydev = dev_get_drvdata(dev);
210 long tmp;
211 int ret;
212
213 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
214 if (ret < 0)
215 return ret;
216 if (!ret)
217 return -ENODATA;
218
219 tmp = (s16)ret;
220 tmp *= 78125;
221 tmp /= 10000;
222
223 *value = tmp;
224
225 return 0;
226 }
227
gpy_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)228 static umode_t gpy_hwmon_is_visible(const void *data,
229 enum hwmon_sensor_types type,
230 u32 attr, int channel)
231 {
232 return 0444;
233 }
234
235 static const struct hwmon_channel_info * const gpy_hwmon_info[] = {
236 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
237 NULL
238 };
239
240 static const struct hwmon_ops gpy_hwmon_hwmon_ops = {
241 .is_visible = gpy_hwmon_is_visible,
242 .read = gpy_hwmon_read,
243 };
244
245 static const struct hwmon_ops mxl862x2_hwmon_hwmon_ops = {
246 .is_visible = gpy_hwmon_is_visible,
247 .read = mxl862x2_hwmon_read,
248 };
249
250 static const struct hwmon_chip_info gpy_hwmon_chip_info = {
251 .ops = &gpy_hwmon_hwmon_ops,
252 .info = gpy_hwmon_info,
253 };
254
255 static const struct hwmon_chip_info mxl862x2_hwmon_chip_info = {
256 .ops = &mxl862x2_hwmon_hwmon_ops,
257 .info = gpy_hwmon_info,
258 };
259
gpy_hwmon_register(struct phy_device * phydev)260 static int gpy_hwmon_register(struct phy_device *phydev)
261 {
262 struct device *dev = &phydev->mdio.dev;
263 const struct hwmon_chip_info *info;
264 struct device *hwmon_dev;
265
266 if (phy_id_compare_model(phydev->phy_id, PHY_ID_MXL86252) ||
267 phy_id_compare_model(phydev->phy_id, PHY_ID_MXL86282))
268 info = &mxl862x2_hwmon_chip_info;
269 else
270 info = &gpy_hwmon_chip_info;
271
272 hwmon_dev = devm_hwmon_device_register_with_info(dev, NULL, phydev,
273 info, NULL);
274
275 return PTR_ERR_OR_ZERO(hwmon_dev);
276 }
277 #else
gpy_hwmon_register(struct phy_device * phydev)278 static int gpy_hwmon_register(struct phy_device *phydev)
279 {
280 return 0;
281 }
282 #endif
283
gpy_ack_interrupt(struct phy_device * phydev)284 static int gpy_ack_interrupt(struct phy_device *phydev)
285 {
286 int ret;
287
288 /* Clear all pending interrupts */
289 ret = phy_read(phydev, PHY_ISTAT);
290 return ret < 0 ? ret : 0;
291 }
292
gpy_mbox_read(struct phy_device * phydev,u32 addr)293 static int gpy_mbox_read(struct phy_device *phydev, u32 addr)
294 {
295 struct gpy_priv *priv = phydev->priv;
296 int val, ret;
297 u16 cmd;
298
299 mutex_lock(&priv->mbox_lock);
300
301 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
302 addr);
303 if (ret)
304 goto out;
305
306 cmd = VSPEC1_MBOX_CMD_RD;
307 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16);
308
309 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
310 if (ret)
311 goto out;
312
313 /* The mbox read is used in the interrupt workaround. It was observed
314 * that a read might take up to 2.5ms. This is also the time for which
315 * the interrupt line is stuck low. To be on the safe side, poll the
316 * ready bit for 10ms.
317 */
318 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
319 VSPEC1_MBOX_CMD, val,
320 (val & VSPEC1_MBOX_CMD_READY),
321 500, 10000, false);
322 if (ret)
323 goto out;
324
325 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
326
327 out:
328 mutex_unlock(&priv->mbox_lock);
329 return ret;
330 }
331
gpy_config_init(struct phy_device * phydev)332 static int gpy_config_init(struct phy_device *phydev)
333 {
334 /* Nothing to configure. Configuration Requirement Placeholder */
335 return 0;
336 }
337
gpy21x_config_init(struct phy_device * phydev)338 static int gpy21x_config_init(struct phy_device *phydev)
339 {
340 __set_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces);
341 __set_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces);
342
343 return gpy_config_init(phydev);
344 }
345
gpy_probe(struct phy_device * phydev)346 static int gpy_probe(struct phy_device *phydev)
347 {
348 struct device *dev = &phydev->mdio.dev;
349 struct gpy_priv *priv;
350 int fw_version;
351 int ret;
352
353 if (!phydev->is_c45) {
354 ret = phy_get_c45_ids(phydev);
355 if (ret < 0)
356 return ret;
357 }
358
359 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
360 if (!priv)
361 return -ENOMEM;
362 phydev->priv = priv;
363 mutex_init(&priv->mbox_lock);
364
365 if (!device_property_present(dev, "maxlinear,use-broken-interrupts"))
366 phydev->dev_flags |= PHY_F_NO_IRQ;
367
368 fw_version = phy_read(phydev, PHY_FWV);
369 if (fw_version < 0)
370 return fw_version;
371 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version);
372 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version);
373
374 ret = gpy_hwmon_register(phydev);
375 if (ret)
376 return ret;
377
378 /* Show GPY PHY FW version in dmesg */
379 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n",
380 priv->fw_major, priv->fw_minor, fw_version,
381 fw_version & PHY_FWV_REL_MASK ? "" : " test version");
382
383 return 0;
384 }
385
gpy_sgmii_need_reaneg(struct phy_device * phydev)386 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
387 {
388 struct gpy_priv *priv = phydev->priv;
389 size_t i;
390
391 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
392 if (priv->fw_major != ver_need_sgmii_reaneg[i].major)
393 continue;
394 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor)
395 return true;
396 break;
397 }
398
399 return false;
400 }
401
gpy_2500basex_chk(struct phy_device * phydev)402 static bool gpy_2500basex_chk(struct phy_device *phydev)
403 {
404 int ret;
405
406 ret = phy_read(phydev, PHY_MIISTAT);
407 if (ret < 0) {
408 phydev_err(phydev, "Error: MDIO register access failed: %d\n",
409 ret);
410 return false;
411 }
412
413 if (!(ret & PHY_MIISTAT_LS) ||
414 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
415 return false;
416
417 phydev->speed = SPEED_2500;
418 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
419 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
420 VSPEC1_SGMII_CTRL_ANEN, 0);
421 return true;
422 }
423
gpy_sgmii_aneg_en(struct phy_device * phydev)424 static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
425 {
426 int ret;
427
428 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
429 if (ret < 0) {
430 phydev_err(phydev, "Error: MMD register access failed: %d\n",
431 ret);
432 return true;
433 }
434
435 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
436 }
437
gpy_config_mdix(struct phy_device * phydev,u8 ctrl)438 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl)
439 {
440 int ret;
441 u16 val;
442
443 switch (ctrl) {
444 case ETH_TP_MDI_AUTO:
445 val = PHY_CTL1_AMDIX;
446 break;
447 case ETH_TP_MDI_X:
448 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD);
449 break;
450 case ETH_TP_MDI:
451 val = 0;
452 break;
453 default:
454 return 0;
455 }
456
457 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB |
458 PHY_CTL1_MDICD, val);
459 if (ret < 0)
460 return ret;
461
462 return genphy_c45_restart_aneg(phydev);
463 }
464
gpy_config_aneg(struct phy_device * phydev)465 static int gpy_config_aneg(struct phy_device *phydev)
466 {
467 bool changed = false;
468 u32 adv;
469 int ret;
470
471 if (phydev->autoneg == AUTONEG_DISABLE) {
472 /* Configure half duplex with genphy_setup_forced,
473 * because genphy_c45_pma_setup_forced does not support.
474 */
475 return phydev->duplex != DUPLEX_FULL
476 ? genphy_setup_forced(phydev)
477 : genphy_c45_pma_setup_forced(phydev);
478 }
479
480 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl);
481 if (ret < 0)
482 return ret;
483
484 ret = genphy_c45_an_config_aneg(phydev);
485 if (ret < 0)
486 return ret;
487 if (ret > 0)
488 changed = true;
489
490 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
491 ret = phy_modify_changed(phydev, MII_CTRL1000,
492 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
493 adv);
494 if (ret < 0)
495 return ret;
496 if (ret > 0)
497 changed = true;
498
499 ret = genphy_c45_check_and_restart_aneg(phydev, changed);
500 if (ret < 0)
501 return ret;
502
503 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
504 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
505 return 0;
506
507 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
508 * disabled.
509 */
510 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
511 !gpy_sgmii_aneg_en(phydev))
512 return 0;
513
514 /* There is a design constraint in GPY2xx device where SGMII AN is
515 * only triggered when there is change of speed. If, PHY link
516 * partner`s speed is still same even after PHY TPI is down and up
517 * again, SGMII AN is not triggered and hence no new in-band message
518 * from GPY to MAC side SGMII.
519 * This could cause an issue during power up, when PHY is up prior to
520 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
521 * wouldn`t receive new in-band message from GPY with correct link
522 * status, speed and duplex info.
523 *
524 * 1) If PHY is already up and TPI link status is still down (such as
525 * hard reboot), TPI link status is polled for 4 seconds before
526 * retriggerring SGMII AN.
527 * 2) If PHY is already up and TPI link status is also up (such as soft
528 * reboot), polling of TPI link status is not needed and SGMII AN is
529 * immediately retriggered.
530 * 3) Other conditions such as PHY is down, speed change etc, skip
531 * retriggering SGMII AN. Note: in case of speed change, GPY FW will
532 * initiate SGMII AN.
533 */
534
535 if (phydev->state != PHY_UP)
536 return 0;
537
538 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
539 20000, 4000000, false);
540 if (ret == -ETIMEDOUT)
541 return 0;
542 else if (ret < 0)
543 return ret;
544
545 /* Trigger SGMII AN. */
546 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
547 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
548 }
549
gpy_update_mdix(struct phy_device * phydev)550 static int gpy_update_mdix(struct phy_device *phydev)
551 {
552 int ret;
553
554 ret = phy_read(phydev, PHY_CTL1);
555 if (ret < 0)
556 return ret;
557
558 if (ret & PHY_CTL1_AMDIX)
559 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
560 else
561 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB)
562 phydev->mdix_ctrl = ETH_TP_MDI_X;
563 else
564 phydev->mdix_ctrl = ETH_TP_MDI;
565
566 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY);
567 if (ret < 0)
568 return ret;
569
570 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL)
571 phydev->mdix = ETH_TP_MDI_X;
572 else
573 phydev->mdix = ETH_TP_MDI;
574
575 return 0;
576 }
577
gpy_update_interface(struct phy_device * phydev)578 static int gpy_update_interface(struct phy_device *phydev)
579 {
580 int ret;
581
582 /* Interface mode is fixed for USXGMII and integrated PHY */
583 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
584 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
585 return 0;
586
587 /* Automatically switch SERDES interface between SGMII and 2500-BaseX
588 * according to speed. Disable ANEG in 2500-BaseX mode.
589 */
590 switch (phydev->speed) {
591 case SPEED_2500:
592 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
593 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
594 VSPEC1_SGMII_CTRL_ANEN, 0);
595 if (ret < 0) {
596 phydev_err(phydev,
597 "Error: Disable of SGMII ANEG failed: %d\n",
598 ret);
599 return ret;
600 }
601 break;
602 case SPEED_1000:
603 case SPEED_100:
604 case SPEED_10:
605 phydev->interface = PHY_INTERFACE_MODE_SGMII;
606 break;
607 }
608
609 return 0;
610 }
611
gpy_read_status(struct phy_device * phydev)612 static int gpy_read_status(struct phy_device *phydev)
613 {
614 int ret;
615
616 ret = genphy_update_link(phydev);
617 if (ret)
618 return ret;
619
620 phydev->speed = SPEED_UNKNOWN;
621 phydev->duplex = DUPLEX_UNKNOWN;
622 phydev->pause = 0;
623 phydev->asym_pause = 0;
624
625 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
626 ret = genphy_c45_read_lpa(phydev);
627 if (ret < 0)
628 return ret;
629
630 /* Read the link partner's 1G advertisement */
631 ret = phy_read(phydev, MII_STAT1000);
632 if (ret < 0)
633 return ret;
634 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
635 } else if (phydev->autoneg == AUTONEG_DISABLE) {
636 linkmode_zero(phydev->lp_advertising);
637 }
638
639 ret = phy_read(phydev, PHY_MIISTAT);
640 if (ret < 0)
641 return ret;
642
643 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
644 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
645 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) {
646 case PHY_MIISTAT_SPD_10:
647 phydev->speed = SPEED_10;
648 break;
649 case PHY_MIISTAT_SPD_100:
650 phydev->speed = SPEED_100;
651 break;
652 case PHY_MIISTAT_SPD_1000:
653 phydev->speed = SPEED_1000;
654 break;
655 case PHY_MIISTAT_SPD_2500:
656 phydev->speed = SPEED_2500;
657 break;
658 }
659
660 if (phydev->link) {
661 ret = gpy_update_interface(phydev);
662 if (ret < 0)
663 return ret;
664
665 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) {
666 ret = genphy_read_master_slave(phydev);
667 if (ret < 0)
668 return ret;
669 }
670
671 ret = gpy_update_mdix(phydev);
672 if (ret < 0)
673 return ret;
674 }
675
676 return 0;
677 }
678
gpy_config_intr(struct phy_device * phydev)679 static int gpy_config_intr(struct phy_device *phydev)
680 {
681 struct gpy_priv *priv = phydev->priv;
682 u16 mask = 0;
683 int ret;
684
685 ret = gpy_ack_interrupt(phydev);
686 if (ret)
687 return ret;
688
689 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
690 mask = PHY_IMASK_MASK;
691
692 if (priv->wolopts & WAKE_MAGIC)
693 mask |= PHY_IMASK_WOL;
694
695 if (priv->wolopts & WAKE_PHY)
696 mask |= PHY_IMASK_LSTC;
697
698 return phy_write(phydev, PHY_IMASK, mask);
699 }
700
gpy_handle_interrupt(struct phy_device * phydev)701 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev)
702 {
703 int reg;
704
705 reg = phy_read(phydev, PHY_ISTAT);
706 if (reg < 0) {
707 phy_error(phydev);
708 return IRQ_NONE;
709 }
710
711 if (!(reg & PHY_IMASK_MASK))
712 return IRQ_NONE;
713
714 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT
715 * is read. To avoid interrupt storms, delay the interrupt handling as
716 * long as the PHY drives the interrupt line. An internal bus read will
717 * stall as long as the interrupt line is asserted, thus just read a
718 * random register here.
719 * Because we cannot access the internal bus at all while the interrupt
720 * is driven by the PHY, there is no way to make the interrupt line
721 * unstuck (e.g. by changing the pinmux to GPIO input) during that time
722 * frame. Therefore, polling is the best we can do and won't do any more
723 * harm.
724 * It was observed that this bug happens on link state and link speed
725 * changes independent of the firmware version.
726 */
727 if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) {
728 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT);
729 if (reg < 0) {
730 phy_error(phydev);
731 return IRQ_NONE;
732 }
733 }
734
735 phy_trigger_machine(phydev);
736
737 return IRQ_HANDLED;
738 }
739
gpy_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)740 static int gpy_set_wol(struct phy_device *phydev,
741 struct ethtool_wolinfo *wol)
742 {
743 struct net_device *attach_dev = phydev->attached_dev;
744 struct gpy_priv *priv = phydev->priv;
745 int ret;
746
747 if (wol->wolopts & WAKE_MAGIC) {
748 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5
749 * VPSPEC2_WOL_AD45 = Byte0:Byte1
750 * VPSPEC2_WOL_AD23 = Byte2:Byte3
751 * VPSPEC2_WOL_AD01 = Byte4:Byte5
752 */
753 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
754 VPSPEC2_WOL_AD45,
755 ((attach_dev->dev_addr[0] << 8) |
756 attach_dev->dev_addr[1]));
757 if (ret < 0)
758 return ret;
759
760 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
761 VPSPEC2_WOL_AD23,
762 ((attach_dev->dev_addr[2] << 8) |
763 attach_dev->dev_addr[3]));
764 if (ret < 0)
765 return ret;
766
767 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
768 VPSPEC2_WOL_AD01,
769 ((attach_dev->dev_addr[4] << 8) |
770 attach_dev->dev_addr[5]));
771 if (ret < 0)
772 return ret;
773
774 /* Enable the WOL interrupt */
775 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL);
776 if (ret < 0)
777 return ret;
778
779 /* Enable magic packet matching */
780 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
781 VPSPEC2_WOL_CTL,
782 WOL_EN);
783 if (ret < 0)
784 return ret;
785
786 /* Clear the interrupt status register.
787 * Only WoL is enabled so clear all.
788 */
789 ret = phy_read(phydev, PHY_ISTAT);
790 if (ret < 0)
791 return ret;
792
793 priv->wolopts |= WAKE_MAGIC;
794 } else {
795 /* Disable magic packet matching */
796 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
797 VPSPEC2_WOL_CTL,
798 WOL_EN);
799 if (ret < 0)
800 return ret;
801
802 /* Disable the WOL interrupt */
803 ret = phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_WOL);
804 if (ret < 0)
805 return ret;
806
807 priv->wolopts &= ~WAKE_MAGIC;
808 }
809
810 if (wol->wolopts & WAKE_PHY) {
811 /* Enable the link state change interrupt */
812 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
813 if (ret < 0)
814 return ret;
815
816 /* Clear the interrupt status register */
817 ret = phy_read(phydev, PHY_ISTAT);
818 if (ret < 0)
819 return ret;
820
821 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC))
822 phy_trigger_machine(phydev);
823
824 priv->wolopts |= WAKE_PHY;
825 return 0;
826 }
827
828 priv->wolopts &= ~WAKE_PHY;
829 /* Disable the link state change interrupt */
830 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
831 }
832
gpy_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)833 static void gpy_get_wol(struct phy_device *phydev,
834 struct ethtool_wolinfo *wol)
835 {
836 struct gpy_priv *priv = phydev->priv;
837
838 wol->supported = WAKE_MAGIC | WAKE_PHY;
839 wol->wolopts = priv->wolopts;
840 }
841
gpy_loopback(struct phy_device * phydev,bool enable,int speed)842 static int gpy_loopback(struct phy_device *phydev, bool enable, int speed)
843 {
844 struct gpy_priv *priv = phydev->priv;
845 u16 set = 0;
846 int ret;
847
848 if (enable) {
849 u64 now = get_jiffies_64();
850
851 if (speed)
852 return -EOPNOTSUPP;
853
854 /* wait until 3 seconds from last disable */
855 if (time_before64(now, priv->lb_dis_to))
856 msleep(jiffies64_to_msecs(priv->lb_dis_to - now));
857
858 set = BMCR_LOOPBACK;
859 }
860
861 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set);
862 if (ret <= 0)
863 return ret;
864
865 if (enable) {
866 /* It takes some time for PHY device to switch into
867 * loopback mode.
868 */
869 msleep(100);
870 } else {
871 priv->lb_dis_to = get_jiffies_64() + HZ * 3;
872 }
873
874 return 0;
875 }
876
gpy115_loopback(struct phy_device * phydev,bool enable,int speed)877 static int gpy115_loopback(struct phy_device *phydev, bool enable, int speed)
878 {
879 struct gpy_priv *priv = phydev->priv;
880
881 if (enable)
882 return gpy_loopback(phydev, enable, speed);
883
884 if (priv->fw_minor > 0x76)
885 return gpy_loopback(phydev, 0, 0);
886
887 return genphy_soft_reset(phydev);
888 }
889
gpy_led_brightness_set(struct phy_device * phydev,u8 index,enum led_brightness value)890 static int gpy_led_brightness_set(struct phy_device *phydev,
891 u8 index, enum led_brightness value)
892 {
893 int ret;
894
895 if (index >= GPY_MAX_LEDS)
896 return -EINVAL;
897
898 /* clear HWCONTROL and set manual LED state */
899 ret = phy_modify(phydev, PHY_LED,
900 ((value == LED_OFF) ? PHY_LED_HWCONTROL(index) : 0) |
901 PHY_LED_ON(index),
902 (value == LED_OFF) ? 0 : PHY_LED_ON(index));
903 if (ret)
904 return ret;
905
906 /* ToDo: set PWM brightness */
907
908 /* clear HW LED setup */
909 if (value == LED_OFF)
910 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), 0);
911 else
912 return 0;
913 }
914
915 static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) |
916 BIT(TRIGGER_NETDEV_LINK_10) |
917 BIT(TRIGGER_NETDEV_LINK_100) |
918 BIT(TRIGGER_NETDEV_LINK_1000) |
919 BIT(TRIGGER_NETDEV_LINK_2500) |
920 BIT(TRIGGER_NETDEV_RX) |
921 BIT(TRIGGER_NETDEV_TX));
922
gpy_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)923 static int gpy_led_hw_is_supported(struct phy_device *phydev, u8 index,
924 unsigned long rules)
925 {
926 if (index >= GPY_MAX_LEDS)
927 return -EINVAL;
928
929 /* All combinations of the supported triggers are allowed */
930 if (rules & ~supported_triggers)
931 return -EOPNOTSUPP;
932
933 return 0;
934 }
935
gpy_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)936 static int gpy_led_hw_control_get(struct phy_device *phydev, u8 index,
937 unsigned long *rules)
938 {
939 int val;
940
941 if (index >= GPY_MAX_LEDS)
942 return -EINVAL;
943
944 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index));
945 if (val < 0)
946 return val;
947
948 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK10)
949 *rules |= BIT(TRIGGER_NETDEV_LINK_10);
950
951 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK100)
952 *rules |= BIT(TRIGGER_NETDEV_LINK_100);
953
954 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK1000)
955 *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
956
957 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK2500)
958 *rules |= BIT(TRIGGER_NETDEV_LINK_2500);
959
960 if (FIELD_GET(VSPEC1_LED_CON, val) == (VSPEC1_LED_LINK10 |
961 VSPEC1_LED_LINK100 |
962 VSPEC1_LED_LINK1000 |
963 VSPEC1_LED_LINK2500))
964 *rules |= BIT(TRIGGER_NETDEV_LINK);
965
966 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_TXACT)
967 *rules |= BIT(TRIGGER_NETDEV_TX);
968
969 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_RXACT)
970 *rules |= BIT(TRIGGER_NETDEV_RX);
971
972 return 0;
973 }
974
gpy_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)975 static int gpy_led_hw_control_set(struct phy_device *phydev, u8 index,
976 unsigned long rules)
977 {
978 u16 val = 0;
979 int ret;
980
981 if (index >= GPY_MAX_LEDS)
982 return -EINVAL;
983
984 if (rules & BIT(TRIGGER_NETDEV_LINK) ||
985 rules & BIT(TRIGGER_NETDEV_LINK_10))
986 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK10);
987
988 if (rules & BIT(TRIGGER_NETDEV_LINK) ||
989 rules & BIT(TRIGGER_NETDEV_LINK_100))
990 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK100);
991
992 if (rules & BIT(TRIGGER_NETDEV_LINK) ||
993 rules & BIT(TRIGGER_NETDEV_LINK_1000))
994 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK1000);
995
996 if (rules & BIT(TRIGGER_NETDEV_LINK) ||
997 rules & BIT(TRIGGER_NETDEV_LINK_2500))
998 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK2500);
999
1000 if (rules & BIT(TRIGGER_NETDEV_TX))
1001 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_TXACT);
1002
1003 if (rules & BIT(TRIGGER_NETDEV_RX))
1004 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_RXACT);
1005
1006 /* allow RX/TX pulse without link indication */
1007 if ((rules & BIT(TRIGGER_NETDEV_TX) || rules & BIT(TRIGGER_NETDEV_RX)) &&
1008 !(val & VSPEC1_LED_CON))
1009 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_NO_CON) | VSPEC1_LED_CON;
1010
1011 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), val);
1012 if (ret)
1013 return ret;
1014
1015 return phy_set_bits(phydev, PHY_LED, PHY_LED_HWCONTROL(index));
1016 }
1017
gpy_led_polarity_set(struct phy_device * phydev,int index,unsigned long modes)1018 static int gpy_led_polarity_set(struct phy_device *phydev, int index,
1019 unsigned long modes)
1020 {
1021 bool force_active_low = false, force_active_high = false;
1022 u32 mode;
1023
1024 if (index >= GPY_MAX_LEDS)
1025 return -EINVAL;
1026
1027 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
1028 switch (mode) {
1029 case PHY_LED_ACTIVE_LOW:
1030 force_active_low = true;
1031 break;
1032 case PHY_LED_ACTIVE_HIGH:
1033 force_active_high = true;
1034 break;
1035 default:
1036 return -EINVAL;
1037 }
1038 }
1039
1040 if (force_active_low)
1041 return phy_set_bits(phydev, PHY_LED, PHY_LED_POLARITY(index));
1042
1043 if (force_active_high)
1044 return phy_clear_bits(phydev, PHY_LED, PHY_LED_POLARITY(index));
1045
1046 return -EINVAL;
1047 }
1048
gpy_inband_caps(struct phy_device * phydev,phy_interface_t interface)1049 static unsigned int gpy_inband_caps(struct phy_device *phydev,
1050 phy_interface_t interface)
1051 {
1052 switch (interface) {
1053 case PHY_INTERFACE_MODE_SGMII:
1054 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
1055 case PHY_INTERFACE_MODE_2500BASEX:
1056 return LINK_INBAND_DISABLE;
1057 default:
1058 return 0;
1059 }
1060 }
1061
gpy_config_inband(struct phy_device * phydev,unsigned int modes)1062 static int gpy_config_inband(struct phy_device *phydev, unsigned int modes)
1063 {
1064 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
1065 VSPEC1_SGMII_ANEN_ANRS,
1066 (modes == LINK_INBAND_DISABLE) ? 0 :
1067 VSPEC1_SGMII_ANEN_ANRS);
1068 }
1069
1070 static struct phy_driver gpy_drivers[] = {
1071 {
1072 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx),
1073 .name = "Maxlinear Ethernet GPY2xx",
1074 .get_features = genphy_c45_pma_read_abilities,
1075 .config_init = gpy_config_init,
1076 .probe = gpy_probe,
1077 .inband_caps = gpy_inband_caps,
1078 .config_inband = gpy_config_inband,
1079 .suspend = genphy_suspend,
1080 .resume = genphy_resume,
1081 .config_aneg = gpy_config_aneg,
1082 .aneg_done = genphy_c45_aneg_done,
1083 .read_status = gpy_read_status,
1084 .config_intr = gpy_config_intr,
1085 .handle_interrupt = gpy_handle_interrupt,
1086 .set_wol = gpy_set_wol,
1087 .get_wol = gpy_get_wol,
1088 .set_loopback = gpy_loopback,
1089 .led_brightness_set = gpy_led_brightness_set,
1090 .led_hw_is_supported = gpy_led_hw_is_supported,
1091 .led_hw_control_get = gpy_led_hw_control_get,
1092 .led_hw_control_set = gpy_led_hw_control_set,
1093 .led_polarity_set = gpy_led_polarity_set,
1094 },
1095 {
1096 .phy_id = PHY_ID_GPY115B,
1097 .phy_id_mask = PHY_ID_GPYx15B_MASK,
1098 .name = "Maxlinear Ethernet GPY115B",
1099 .get_features = genphy_c45_pma_read_abilities,
1100 .config_init = gpy_config_init,
1101 .probe = gpy_probe,
1102 .inband_caps = gpy_inband_caps,
1103 .config_inband = gpy_config_inband,
1104 .suspend = genphy_suspend,
1105 .resume = genphy_resume,
1106 .config_aneg = gpy_config_aneg,
1107 .aneg_done = genphy_c45_aneg_done,
1108 .read_status = gpy_read_status,
1109 .config_intr = gpy_config_intr,
1110 .handle_interrupt = gpy_handle_interrupt,
1111 .set_wol = gpy_set_wol,
1112 .get_wol = gpy_get_wol,
1113 .set_loopback = gpy115_loopback,
1114 .led_brightness_set = gpy_led_brightness_set,
1115 .led_hw_is_supported = gpy_led_hw_is_supported,
1116 .led_hw_control_get = gpy_led_hw_control_get,
1117 .led_hw_control_set = gpy_led_hw_control_set,
1118 .led_polarity_set = gpy_led_polarity_set,
1119 },
1120 {
1121 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C),
1122 .name = "Maxlinear Ethernet GPY115C",
1123 .get_features = genphy_c45_pma_read_abilities,
1124 .config_init = gpy_config_init,
1125 .probe = gpy_probe,
1126 .inband_caps = gpy_inband_caps,
1127 .config_inband = gpy_config_inband,
1128 .suspend = genphy_suspend,
1129 .resume = genphy_resume,
1130 .config_aneg = gpy_config_aneg,
1131 .aneg_done = genphy_c45_aneg_done,
1132 .read_status = gpy_read_status,
1133 .config_intr = gpy_config_intr,
1134 .handle_interrupt = gpy_handle_interrupt,
1135 .set_wol = gpy_set_wol,
1136 .get_wol = gpy_get_wol,
1137 .set_loopback = gpy115_loopback,
1138 .led_brightness_set = gpy_led_brightness_set,
1139 .led_hw_is_supported = gpy_led_hw_is_supported,
1140 .led_hw_control_get = gpy_led_hw_control_get,
1141 .led_hw_control_set = gpy_led_hw_control_set,
1142 .led_polarity_set = gpy_led_polarity_set,
1143 },
1144 {
1145 .phy_id = PHY_ID_GPY211B,
1146 .phy_id_mask = PHY_ID_GPY21xB_MASK,
1147 .name = "Maxlinear Ethernet GPY211B",
1148 .get_features = genphy_c45_pma_read_abilities,
1149 .config_init = gpy21x_config_init,
1150 .probe = gpy_probe,
1151 .inband_caps = gpy_inband_caps,
1152 .config_inband = gpy_config_inband,
1153 .suspend = genphy_suspend,
1154 .resume = genphy_resume,
1155 .config_aneg = gpy_config_aneg,
1156 .aneg_done = genphy_c45_aneg_done,
1157 .read_status = gpy_read_status,
1158 .config_intr = gpy_config_intr,
1159 .handle_interrupt = gpy_handle_interrupt,
1160 .set_wol = gpy_set_wol,
1161 .get_wol = gpy_get_wol,
1162 .set_loopback = gpy_loopback,
1163 .led_brightness_set = gpy_led_brightness_set,
1164 .led_hw_is_supported = gpy_led_hw_is_supported,
1165 .led_hw_control_get = gpy_led_hw_control_get,
1166 .led_hw_control_set = gpy_led_hw_control_set,
1167 .led_polarity_set = gpy_led_polarity_set,
1168 },
1169 {
1170 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C),
1171 .name = "Maxlinear Ethernet GPY211C",
1172 .get_features = genphy_c45_pma_read_abilities,
1173 .config_init = gpy21x_config_init,
1174 .probe = gpy_probe,
1175 .inband_caps = gpy_inband_caps,
1176 .config_inband = gpy_config_inband,
1177 .suspend = genphy_suspend,
1178 .resume = genphy_resume,
1179 .config_aneg = gpy_config_aneg,
1180 .aneg_done = genphy_c45_aneg_done,
1181 .read_status = gpy_read_status,
1182 .config_intr = gpy_config_intr,
1183 .handle_interrupt = gpy_handle_interrupt,
1184 .set_wol = gpy_set_wol,
1185 .get_wol = gpy_get_wol,
1186 .set_loopback = gpy_loopback,
1187 .led_brightness_set = gpy_led_brightness_set,
1188 .led_hw_is_supported = gpy_led_hw_is_supported,
1189 .led_hw_control_get = gpy_led_hw_control_get,
1190 .led_hw_control_set = gpy_led_hw_control_set,
1191 .led_polarity_set = gpy_led_polarity_set,
1192 },
1193 {
1194 .phy_id = PHY_ID_GPY212B,
1195 .phy_id_mask = PHY_ID_GPY21xB_MASK,
1196 .name = "Maxlinear Ethernet GPY212B",
1197 .get_features = genphy_c45_pma_read_abilities,
1198 .config_init = gpy21x_config_init,
1199 .inband_caps = gpy_inband_caps,
1200 .config_inband = gpy_config_inband,
1201 .probe = gpy_probe,
1202 .suspend = genphy_suspend,
1203 .resume = genphy_resume,
1204 .config_aneg = gpy_config_aneg,
1205 .aneg_done = genphy_c45_aneg_done,
1206 .read_status = gpy_read_status,
1207 .config_intr = gpy_config_intr,
1208 .handle_interrupt = gpy_handle_interrupt,
1209 .set_wol = gpy_set_wol,
1210 .get_wol = gpy_get_wol,
1211 .set_loopback = gpy_loopback,
1212 .led_brightness_set = gpy_led_brightness_set,
1213 .led_hw_is_supported = gpy_led_hw_is_supported,
1214 .led_hw_control_get = gpy_led_hw_control_get,
1215 .led_hw_control_set = gpy_led_hw_control_set,
1216 .led_polarity_set = gpy_led_polarity_set,
1217 },
1218 {
1219 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C),
1220 .name = "Maxlinear Ethernet GPY212C",
1221 .get_features = genphy_c45_pma_read_abilities,
1222 .config_init = gpy21x_config_init,
1223 .probe = gpy_probe,
1224 .inband_caps = gpy_inband_caps,
1225 .config_inband = gpy_config_inband,
1226 .suspend = genphy_suspend,
1227 .resume = genphy_resume,
1228 .config_aneg = gpy_config_aneg,
1229 .aneg_done = genphy_c45_aneg_done,
1230 .read_status = gpy_read_status,
1231 .config_intr = gpy_config_intr,
1232 .handle_interrupt = gpy_handle_interrupt,
1233 .set_wol = gpy_set_wol,
1234 .get_wol = gpy_get_wol,
1235 .set_loopback = gpy_loopback,
1236 .led_brightness_set = gpy_led_brightness_set,
1237 .led_hw_is_supported = gpy_led_hw_is_supported,
1238 .led_hw_control_get = gpy_led_hw_control_get,
1239 .led_hw_control_set = gpy_led_hw_control_set,
1240 .led_polarity_set = gpy_led_polarity_set,
1241 },
1242 {
1243 .phy_id = PHY_ID_GPY215B,
1244 .phy_id_mask = PHY_ID_GPYx15B_MASK,
1245 .name = "Maxlinear Ethernet GPY215B",
1246 .get_features = genphy_c45_pma_read_abilities,
1247 .config_init = gpy21x_config_init,
1248 .probe = gpy_probe,
1249 .inband_caps = gpy_inband_caps,
1250 .config_inband = gpy_config_inband,
1251 .suspend = genphy_suspend,
1252 .resume = genphy_resume,
1253 .config_aneg = gpy_config_aneg,
1254 .aneg_done = genphy_c45_aneg_done,
1255 .read_status = gpy_read_status,
1256 .config_intr = gpy_config_intr,
1257 .handle_interrupt = gpy_handle_interrupt,
1258 .set_wol = gpy_set_wol,
1259 .get_wol = gpy_get_wol,
1260 .set_loopback = gpy_loopback,
1261 .led_brightness_set = gpy_led_brightness_set,
1262 .led_hw_is_supported = gpy_led_hw_is_supported,
1263 .led_hw_control_get = gpy_led_hw_control_get,
1264 .led_hw_control_set = gpy_led_hw_control_set,
1265 .led_polarity_set = gpy_led_polarity_set,
1266 },
1267 {
1268 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C),
1269 .name = "Maxlinear Ethernet GPY215C",
1270 .get_features = genphy_c45_pma_read_abilities,
1271 .config_init = gpy21x_config_init,
1272 .probe = gpy_probe,
1273 .inband_caps = gpy_inband_caps,
1274 .config_inband = gpy_config_inband,
1275 .suspend = genphy_suspend,
1276 .resume = genphy_resume,
1277 .config_aneg = gpy_config_aneg,
1278 .aneg_done = genphy_c45_aneg_done,
1279 .read_status = gpy_read_status,
1280 .config_intr = gpy_config_intr,
1281 .handle_interrupt = gpy_handle_interrupt,
1282 .set_wol = gpy_set_wol,
1283 .get_wol = gpy_get_wol,
1284 .set_loopback = gpy_loopback,
1285 .led_brightness_set = gpy_led_brightness_set,
1286 .led_hw_is_supported = gpy_led_hw_is_supported,
1287 .led_hw_control_get = gpy_led_hw_control_get,
1288 .led_hw_control_set = gpy_led_hw_control_set,
1289 .led_polarity_set = gpy_led_polarity_set,
1290 },
1291 {
1292 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B),
1293 .name = "Maxlinear Ethernet GPY241B",
1294 .get_features = genphy_c45_pma_read_abilities,
1295 .config_init = gpy_config_init,
1296 .probe = gpy_probe,
1297 .inband_caps = gpy_inband_caps,
1298 .config_inband = gpy_config_inband,
1299 .suspend = genphy_suspend,
1300 .resume = genphy_resume,
1301 .config_aneg = gpy_config_aneg,
1302 .aneg_done = genphy_c45_aneg_done,
1303 .read_status = gpy_read_status,
1304 .config_intr = gpy_config_intr,
1305 .handle_interrupt = gpy_handle_interrupt,
1306 .set_wol = gpy_set_wol,
1307 .get_wol = gpy_get_wol,
1308 .set_loopback = gpy_loopback,
1309 },
1310 {
1311 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM),
1312 .name = "Maxlinear Ethernet GPY241BM",
1313 .get_features = genphy_c45_pma_read_abilities,
1314 .config_init = gpy_config_init,
1315 .probe = gpy_probe,
1316 .inband_caps = gpy_inband_caps,
1317 .config_inband = gpy_config_inband,
1318 .suspend = genphy_suspend,
1319 .resume = genphy_resume,
1320 .config_aneg = gpy_config_aneg,
1321 .aneg_done = genphy_c45_aneg_done,
1322 .read_status = gpy_read_status,
1323 .config_intr = gpy_config_intr,
1324 .handle_interrupt = gpy_handle_interrupt,
1325 .set_wol = gpy_set_wol,
1326 .get_wol = gpy_get_wol,
1327 .set_loopback = gpy_loopback,
1328 },
1329 {
1330 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B),
1331 .name = "Maxlinear Ethernet GPY245B",
1332 .get_features = genphy_c45_pma_read_abilities,
1333 .config_init = gpy_config_init,
1334 .probe = gpy_probe,
1335 .inband_caps = gpy_inband_caps,
1336 .config_inband = gpy_config_inband,
1337 .suspend = genphy_suspend,
1338 .resume = genphy_resume,
1339 .config_aneg = gpy_config_aneg,
1340 .aneg_done = genphy_c45_aneg_done,
1341 .read_status = gpy_read_status,
1342 .config_intr = gpy_config_intr,
1343 .handle_interrupt = gpy_handle_interrupt,
1344 .set_wol = gpy_set_wol,
1345 .get_wol = gpy_get_wol,
1346 .set_loopback = gpy_loopback,
1347 },
1348 {
1349 PHY_ID_MATCH_MODEL(PHY_ID_MXL86211C),
1350 .name = "Maxlinear Ethernet MxL86211C",
1351 .get_features = genphy_c45_pma_read_abilities,
1352 .config_init = gpy_config_init,
1353 .probe = gpy_probe,
1354 .inband_caps = gpy_inband_caps,
1355 .config_inband = gpy_config_inband,
1356 .suspend = genphy_suspend,
1357 .resume = genphy_resume,
1358 .config_aneg = gpy_config_aneg,
1359 .aneg_done = genphy_c45_aneg_done,
1360 .read_status = gpy_read_status,
1361 .config_intr = gpy_config_intr,
1362 .handle_interrupt = gpy_handle_interrupt,
1363 .set_wol = gpy_set_wol,
1364 .get_wol = gpy_get_wol,
1365 .set_loopback = gpy_loopback,
1366 .led_brightness_set = gpy_led_brightness_set,
1367 .led_hw_is_supported = gpy_led_hw_is_supported,
1368 .led_hw_control_get = gpy_led_hw_control_get,
1369 .led_hw_control_set = gpy_led_hw_control_set,
1370 .led_polarity_set = gpy_led_polarity_set,
1371 },
1372 {
1373 PHY_ID_MATCH_MODEL(PHY_ID_MXL86252),
1374 .name = "MaxLinear Ethernet MxL86252",
1375 .get_features = genphy_c45_pma_read_abilities,
1376 .config_init = gpy_config_init,
1377 .probe = gpy_probe,
1378 .suspend = genphy_suspend,
1379 .resume = genphy_resume,
1380 .config_aneg = gpy_config_aneg,
1381 .aneg_done = genphy_c45_aneg_done,
1382 .read_status = gpy_read_status,
1383 .config_intr = gpy_config_intr,
1384 .handle_interrupt = gpy_handle_interrupt,
1385 .set_wol = gpy_set_wol,
1386 .get_wol = gpy_get_wol,
1387 .set_loopback = gpy_loopback,
1388 .led_brightness_set = gpy_led_brightness_set,
1389 .led_hw_is_supported = gpy_led_hw_is_supported,
1390 .led_hw_control_get = gpy_led_hw_control_get,
1391 .led_hw_control_set = gpy_led_hw_control_set,
1392 .led_polarity_set = gpy_led_polarity_set,
1393 },
1394 {
1395 PHY_ID_MATCH_MODEL(PHY_ID_MXL86282),
1396 .name = "MaxLinear Ethernet MxL86282",
1397 .get_features = genphy_c45_pma_read_abilities,
1398 .config_init = gpy_config_init,
1399 .probe = gpy_probe,
1400 .suspend = genphy_suspend,
1401 .resume = genphy_resume,
1402 .config_aneg = gpy_config_aneg,
1403 .aneg_done = genphy_c45_aneg_done,
1404 .read_status = gpy_read_status,
1405 .config_intr = gpy_config_intr,
1406 .handle_interrupt = gpy_handle_interrupt,
1407 .set_wol = gpy_set_wol,
1408 .get_wol = gpy_get_wol,
1409 .set_loopback = gpy_loopback,
1410 .led_brightness_set = gpy_led_brightness_set,
1411 .led_hw_is_supported = gpy_led_hw_is_supported,
1412 .led_hw_control_get = gpy_led_hw_control_get,
1413 .led_hw_control_set = gpy_led_hw_control_set,
1414 .led_polarity_set = gpy_led_polarity_set,
1415 },
1416 };
1417 module_phy_driver(gpy_drivers);
1418
1419 static const struct mdio_device_id __maybe_unused gpy_tbl[] = {
1420 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)},
1421 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK},
1422 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)},
1423 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK},
1424 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)},
1425 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK},
1426 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)},
1427 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK},
1428 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)},
1429 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)},
1430 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)},
1431 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)},
1432 {PHY_ID_MATCH_MODEL(PHY_ID_MXL86211C)},
1433 {PHY_ID_MATCH_MODEL(PHY_ID_MXL86252)},
1434 {PHY_ID_MATCH_MODEL(PHY_ID_MXL86282)},
1435 { }
1436 };
1437 MODULE_DEVICE_TABLE(mdio, gpy_tbl);
1438
1439 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver");
1440 MODULE_AUTHOR("Xu Liang");
1441 MODULE_LICENSE("GPL");
1442