1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include <linux/bug.h>
4 #include <linux/aperture.h>
5 #include <linux/module.h>
6 #include <linux/pci.h>
7
8 #include <drm/clients/drm_client_setup.h>
9 #include <drm/drm_atomic.h>
10 #include <drm/drm_atomic_helper.h>
11 #include <drm/drm_damage_helper.h>
12 #include <drm/drm_drv.h>
13 #include <drm/drm_edid.h>
14 #include <drm/drm_fbdev_shmem.h>
15 #include <drm/drm_fourcc.h>
16 #include <drm/drm_framebuffer.h>
17 #include <drm/drm_gem_atomic_helper.h>
18 #include <drm/drm_gem_framebuffer_helper.h>
19 #include <drm/drm_gem_shmem_helper.h>
20 #include <drm/drm_managed.h>
21 #include <drm/drm_module.h>
22 #include <drm/drm_panic.h>
23 #include <drm/drm_plane_helper.h>
24 #include <drm/drm_probe_helper.h>
25
26 #include <video/vga.h>
27
28 /* ---------------------------------------------------------------------- */
29
30 #define VBE_DISPI_IOPORT_INDEX 0x01CE
31 #define VBE_DISPI_IOPORT_DATA 0x01CF
32
33 #define VBE_DISPI_INDEX_ID 0x0
34 #define VBE_DISPI_INDEX_XRES 0x1
35 #define VBE_DISPI_INDEX_YRES 0x2
36 #define VBE_DISPI_INDEX_BPP 0x3
37 #define VBE_DISPI_INDEX_ENABLE 0x4
38 #define VBE_DISPI_INDEX_BANK 0x5
39 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
40 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
41 #define VBE_DISPI_INDEX_X_OFFSET 0x8
42 #define VBE_DISPI_INDEX_Y_OFFSET 0x9
43 #define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa
44
45 #define VBE_DISPI_ID0 0xB0C0
46 #define VBE_DISPI_ID1 0xB0C1
47 #define VBE_DISPI_ID2 0xB0C2
48 #define VBE_DISPI_ID3 0xB0C3
49 #define VBE_DISPI_ID4 0xB0C4
50 #define VBE_DISPI_ID5 0xB0C5
51
52 #define VBE_DISPI_DISABLED 0x00
53 #define VBE_DISPI_ENABLED 0x01
54 #define VBE_DISPI_GETCAPS 0x02
55 #define VBE_DISPI_8BIT_DAC 0x20
56 #define VBE_DISPI_LFB_ENABLED 0x40
57 #define VBE_DISPI_NOCLEARMEM 0x80
58
59 static int bochs_modeset = -1;
60 static int defx = 1024;
61 static int defy = 768;
62
63 module_param_named(modeset, bochs_modeset, int, 0444);
64 MODULE_PARM_DESC(modeset, "enable/disable kernel modesetting");
65
66 module_param(defx, int, 0444);
67 module_param(defy, int, 0444);
68 MODULE_PARM_DESC(defx, "default x resolution");
69 MODULE_PARM_DESC(defy, "default y resolution");
70
71 /* ---------------------------------------------------------------------- */
72
73 enum bochs_types {
74 BOCHS_QEMU_STDVGA,
75 BOCHS_SIMICS,
76 BOCHS_UNKNOWN,
77 };
78
79 struct bochs_device {
80 struct drm_device dev;
81
82 /* hw */
83 void __iomem *mmio;
84 int ioports;
85 void __iomem *fb_map;
86 unsigned long fb_base;
87 unsigned long fb_size;
88 unsigned long qext_size;
89
90 /* mode */
91 u16 xres;
92 u16 yres;
93 u16 yres_virtual;
94 u32 stride;
95 u32 bpp;
96
97 /* drm */
98 struct drm_plane primary_plane;
99 struct drm_crtc crtc;
100 struct drm_encoder encoder;
101 struct drm_connector connector;
102 };
103
to_bochs_device(const struct drm_device * dev)104 static struct bochs_device *to_bochs_device(const struct drm_device *dev)
105 {
106 return container_of(dev, struct bochs_device, dev);
107 }
108
109 /* ---------------------------------------------------------------------- */
110
bochs_uses_mmio(struct bochs_device * bochs)111 static __always_inline bool bochs_uses_mmio(struct bochs_device *bochs)
112 {
113 return !IS_ENABLED(CONFIG_HAS_IOPORT) || bochs->mmio;
114 }
115
bochs_vga_writeb(struct bochs_device * bochs,u16 ioport,u8 val)116 static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val)
117 {
118 if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
119 return;
120
121 if (bochs_uses_mmio(bochs)) {
122 int offset = ioport - 0x3c0 + 0x400;
123
124 writeb(val, bochs->mmio + offset);
125 } else {
126 outb(val, ioport);
127 }
128 }
129
bochs_vga_readb(struct bochs_device * bochs,u16 ioport)130 static u8 bochs_vga_readb(struct bochs_device *bochs, u16 ioport)
131 {
132 if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
133 return 0xff;
134
135 if (bochs_uses_mmio(bochs)) {
136 int offset = ioport - 0x3c0 + 0x400;
137
138 return readb(bochs->mmio + offset);
139 } else {
140 return inb(ioport);
141 }
142 }
143
bochs_dispi_read(struct bochs_device * bochs,u16 reg)144 static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg)
145 {
146 u16 ret = 0;
147
148 if (bochs_uses_mmio(bochs)) {
149 int offset = 0x500 + (reg << 1);
150
151 ret = readw(bochs->mmio + offset);
152 } else {
153 outw(reg, VBE_DISPI_IOPORT_INDEX);
154 ret = inw(VBE_DISPI_IOPORT_DATA);
155 }
156 return ret;
157 }
158
bochs_dispi_write(struct bochs_device * bochs,u16 reg,u16 val)159 static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val)
160 {
161 if (bochs_uses_mmio(bochs)) {
162 int offset = 0x500 + (reg << 1);
163
164 writew(val, bochs->mmio + offset);
165 } else {
166 outw(reg, VBE_DISPI_IOPORT_INDEX);
167 outw(val, VBE_DISPI_IOPORT_DATA);
168 }
169 }
170
bochs_hw_set_big_endian(struct bochs_device * bochs)171 static void bochs_hw_set_big_endian(struct bochs_device *bochs)
172 {
173 if (bochs->qext_size < 8)
174 return;
175
176 writel(0xbebebebe, bochs->mmio + 0x604);
177 }
178
bochs_hw_set_little_endian(struct bochs_device * bochs)179 static void bochs_hw_set_little_endian(struct bochs_device *bochs)
180 {
181 if (bochs->qext_size < 8)
182 return;
183
184 writel(0x1e1e1e1e, bochs->mmio + 0x604);
185 }
186
187 #ifdef __BIG_ENDIAN
188 #define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b)
189 #else
190 #define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b)
191 #endif
192
bochs_get_edid_block(void * data,u8 * buf,unsigned int block,size_t len)193 static int bochs_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len)
194 {
195 struct bochs_device *bochs = data;
196 size_t i, start = block * EDID_LENGTH;
197
198 if (!bochs->mmio)
199 return -1;
200
201 if (start + len > 0x400 /* vga register offset */)
202 return -1;
203
204 for (i = 0; i < len; i++)
205 buf[i] = readb(bochs->mmio + start + i);
206
207 return 0;
208 }
209
bochs_hw_read_edid(struct drm_connector * connector)210 static const struct drm_edid *bochs_hw_read_edid(struct drm_connector *connector)
211 {
212 struct drm_device *dev = connector->dev;
213 struct bochs_device *bochs = to_bochs_device(dev);
214 u8 header[8];
215
216 /* check header to detect whenever edid support is enabled in qemu */
217 bochs_get_edid_block(bochs, header, 0, ARRAY_SIZE(header));
218 if (drm_edid_header_is_valid(header) != 8)
219 return NULL;
220
221 drm_dbg(dev, "Found EDID data blob.\n");
222
223 return drm_edid_read_custom(connector, bochs_get_edid_block, bochs);
224 }
225
bochs_hw_init(struct bochs_device * bochs)226 static int bochs_hw_init(struct bochs_device *bochs)
227 {
228 struct drm_device *dev = &bochs->dev;
229 struct pci_dev *pdev = to_pci_dev(dev->dev);
230 unsigned long addr, size, mem, ioaddr, iosize;
231 u16 id;
232
233 if (pdev->resource[2].flags & IORESOURCE_MEM) {
234 ioaddr = pci_resource_start(pdev, 2);
235 iosize = pci_resource_len(pdev, 2);
236 /* mmio bar with vga and bochs registers present */
237 if (!devm_request_mem_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) {
238 DRM_ERROR("Cannot request mmio region\n");
239 return -EBUSY;
240 }
241 bochs->mmio = devm_ioremap(&pdev->dev, ioaddr, iosize);
242 if (bochs->mmio == NULL) {
243 DRM_ERROR("Cannot map mmio region\n");
244 return -ENOMEM;
245 }
246 } else if (IS_ENABLED(CONFIG_HAS_IOPORT)) {
247 ioaddr = VBE_DISPI_IOPORT_INDEX;
248 iosize = 2;
249 if (!devm_request_region(&pdev->dev, ioaddr, iosize, "bochs-drm")) {
250 DRM_ERROR("Cannot request ioports\n");
251 return -EBUSY;
252 }
253 bochs->ioports = 1;
254 } else {
255 dev_err(dev->dev, "I/O ports are not supported\n");
256 return -EIO;
257 }
258
259 id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID);
260 mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K)
261 * 64 * 1024;
262 if ((id & 0xfff0) != VBE_DISPI_ID0) {
263 DRM_ERROR("ID mismatch\n");
264 return -ENODEV;
265 }
266
267 if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0)
268 return -ENODEV;
269 addr = pci_resource_start(pdev, 0);
270 size = pci_resource_len(pdev, 0);
271 if (addr == 0)
272 return -ENODEV;
273 if (size != mem) {
274 DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n",
275 size, mem);
276 size = min(size, mem);
277 }
278
279 if (!devm_request_mem_region(&pdev->dev, addr, size, "bochs-drm"))
280 DRM_WARN("Cannot request framebuffer, boot fb still active?\n");
281
282 bochs->fb_map = devm_ioremap_wc(&pdev->dev, addr, size);
283 if (bochs->fb_map == NULL) {
284 DRM_ERROR("Cannot map framebuffer\n");
285 return -ENOMEM;
286 }
287 bochs->fb_base = addr;
288 bochs->fb_size = size;
289
290 DRM_INFO("Found bochs VGA, ID 0x%x.\n", id);
291 DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n",
292 size / 1024, addr,
293 bochs->ioports ? "ioports" : "mmio",
294 ioaddr);
295
296 if (bochs->mmio && pdev->revision >= 2) {
297 bochs->qext_size = readl(bochs->mmio + 0x600);
298 if (bochs->qext_size < 4 || bochs->qext_size > iosize) {
299 bochs->qext_size = 0;
300 goto noext;
301 }
302 DRM_DEBUG("Found qemu ext regs, size %ld\n",
303 bochs->qext_size);
304 bochs_hw_set_native_endian(bochs);
305 }
306
307 noext:
308 return 0;
309 }
310
bochs_hw_blank(struct bochs_device * bochs,bool blank)311 static void bochs_hw_blank(struct bochs_device *bochs, bool blank)
312 {
313 DRM_DEBUG_DRIVER("hw_blank %d\n", blank);
314 /* enable color bit (so VGA_IS1_RC access works) */
315 bochs_vga_writeb(bochs, VGA_MIS_W, VGA_MIS_COLOR);
316 /* discard ar_flip_flop */
317 (void)bochs_vga_readb(bochs, VGA_IS1_RC);
318 /* blank or unblank; we need only update index and set 0x20 */
319 bochs_vga_writeb(bochs, VGA_ATT_W, blank ? 0 : 0x20);
320 }
321
bochs_hw_setmode(struct bochs_device * bochs,struct drm_display_mode * mode)322 static void bochs_hw_setmode(struct bochs_device *bochs, struct drm_display_mode *mode)
323 {
324 int idx;
325
326 if (!drm_dev_enter(&bochs->dev, &idx))
327 return;
328
329 bochs->xres = mode->hdisplay;
330 bochs->yres = mode->vdisplay;
331 bochs->bpp = 32;
332 bochs->stride = mode->hdisplay * (bochs->bpp / 8);
333 bochs->yres_virtual = bochs->fb_size / bochs->stride;
334
335 DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n",
336 bochs->xres, bochs->yres, bochs->bpp,
337 bochs->yres_virtual);
338
339 bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 0);
340 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP, bochs->bpp);
341 bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES, bochs->xres);
342 bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES, bochs->yres);
343 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK, 0);
344 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, bochs->xres);
345 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT,
346 bochs->yres_virtual);
347 bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, 0);
348 bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, 0);
349
350 bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,
351 VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED);
352
353 drm_dev_exit(idx);
354 }
355
bochs_hw_setformat(struct bochs_device * bochs,const struct drm_format_info * format)356 static void bochs_hw_setformat(struct bochs_device *bochs, const struct drm_format_info *format)
357 {
358 int idx;
359
360 if (!drm_dev_enter(&bochs->dev, &idx))
361 return;
362
363 DRM_DEBUG_DRIVER("format %c%c%c%c\n",
364 (format->format >> 0) & 0xff,
365 (format->format >> 8) & 0xff,
366 (format->format >> 16) & 0xff,
367 (format->format >> 24) & 0xff);
368
369 switch (format->format) {
370 case DRM_FORMAT_XRGB8888:
371 bochs_hw_set_little_endian(bochs);
372 break;
373 case DRM_FORMAT_BGRX8888:
374 bochs_hw_set_big_endian(bochs);
375 break;
376 default:
377 /* should not happen */
378 DRM_ERROR("%s: Huh? Got framebuffer format 0x%x",
379 __func__, format->format);
380 break;
381 }
382
383 drm_dev_exit(idx);
384 }
385
bochs_hw_setbase(struct bochs_device * bochs,int x,int y,int stride,u64 addr)386 static void bochs_hw_setbase(struct bochs_device *bochs, int x, int y, int stride, u64 addr)
387 {
388 unsigned long offset;
389 unsigned int vx, vy, vwidth, idx;
390
391 if (!drm_dev_enter(&bochs->dev, &idx))
392 return;
393
394 bochs->stride = stride;
395 offset = (unsigned long)addr +
396 y * bochs->stride +
397 x * (bochs->bpp / 8);
398 vy = offset / bochs->stride;
399 vx = (offset % bochs->stride) * 8 / bochs->bpp;
400 vwidth = stride * 8 / bochs->bpp;
401
402 DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n",
403 x, y, addr, offset, vx, vy);
404 bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth);
405 bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx);
406 bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy);
407
408 drm_dev_exit(idx);
409 }
410
411 /* ---------------------------------------------------------------------- */
412
413 static const uint32_t bochs_primary_plane_formats[] = {
414 DRM_FORMAT_XRGB8888,
415 DRM_FORMAT_BGRX8888,
416 };
417
bochs_primary_plane_helper_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)418 static int bochs_primary_plane_helper_atomic_check(struct drm_plane *plane,
419 struct drm_atomic_state *state)
420 {
421 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
422 struct drm_crtc *new_crtc = new_plane_state->crtc;
423 struct drm_crtc_state *new_crtc_state = NULL;
424 int ret;
425
426 if (new_crtc)
427 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
428
429 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
430 DRM_PLANE_NO_SCALING,
431 DRM_PLANE_NO_SCALING,
432 false, false);
433 if (ret)
434 return ret;
435 else if (!new_plane_state->visible)
436 return 0;
437
438 return 0;
439 }
440
bochs_primary_plane_helper_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)441 static void bochs_primary_plane_helper_atomic_update(struct drm_plane *plane,
442 struct drm_atomic_state *state)
443 {
444 struct drm_device *dev = plane->dev;
445 struct bochs_device *bochs = to_bochs_device(dev);
446 struct drm_plane_state *plane_state = plane->state;
447 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
448 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
449 struct drm_framebuffer *fb = plane_state->fb;
450 struct drm_atomic_helper_damage_iter iter;
451 struct drm_rect damage;
452
453 if (!fb || !bochs->stride)
454 return;
455
456 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
457 drm_atomic_for_each_plane_damage(&iter, &damage) {
458 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(bochs->fb_map);
459
460 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, &damage));
461 drm_fb_memcpy(&dst, fb->pitches, shadow_plane_state->data, fb, &damage);
462 }
463
464 /* Always scanout image at VRAM offset 0 */
465 bochs_hw_setbase(bochs,
466 plane_state->crtc_x,
467 plane_state->crtc_y,
468 fb->pitches[0],
469 0);
470 bochs_hw_setformat(bochs, fb->format);
471 }
472
bochs_primary_plane_helper_get_scanout_buffer(struct drm_plane * plane,struct drm_scanout_buffer * sb)473 static int bochs_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane,
474 struct drm_scanout_buffer *sb)
475 {
476 struct bochs_device *bochs = to_bochs_device(plane->dev);
477 struct iosys_map map = IOSYS_MAP_INIT_VADDR_IOMEM(bochs->fb_map);
478
479 if (plane->state && plane->state->fb) {
480 sb->format = plane->state->fb->format;
481 sb->width = plane->state->fb->width;
482 sb->height = plane->state->fb->height;
483 sb->pitch[0] = plane->state->fb->pitches[0];
484 sb->map[0] = map;
485 return 0;
486 }
487 return -ENODEV;
488 }
489
490 static const struct drm_plane_helper_funcs bochs_primary_plane_helper_funcs = {
491 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
492 .atomic_check = bochs_primary_plane_helper_atomic_check,
493 .atomic_update = bochs_primary_plane_helper_atomic_update,
494 .get_scanout_buffer = bochs_primary_plane_helper_get_scanout_buffer,
495 };
496
497 static const struct drm_plane_funcs bochs_primary_plane_funcs = {
498 .update_plane = drm_atomic_helper_update_plane,
499 .disable_plane = drm_atomic_helper_disable_plane,
500 .destroy = drm_plane_cleanup,
501 DRM_GEM_SHADOW_PLANE_FUNCS
502 };
503
bochs_crtc_helper_mode_set_nofb(struct drm_crtc * crtc)504 static void bochs_crtc_helper_mode_set_nofb(struct drm_crtc *crtc)
505 {
506 struct bochs_device *bochs = to_bochs_device(crtc->dev);
507 struct drm_crtc_state *crtc_state = crtc->state;
508
509 bochs_hw_setmode(bochs, &crtc_state->mode);
510 }
511
bochs_crtc_helper_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)512 static int bochs_crtc_helper_atomic_check(struct drm_crtc *crtc,
513 struct drm_atomic_state *state)
514 {
515 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
516
517 if (!crtc_state->enable)
518 return 0;
519
520 return drm_atomic_helper_check_crtc_primary_plane(crtc_state);
521 }
522
bochs_crtc_helper_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)523 static void bochs_crtc_helper_atomic_enable(struct drm_crtc *crtc,
524 struct drm_atomic_state *state)
525 {
526 struct bochs_device *bochs = to_bochs_device(crtc->dev);
527
528 bochs_hw_blank(bochs, false);
529 }
530
bochs_crtc_helper_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * crtc_state)531 static void bochs_crtc_helper_atomic_disable(struct drm_crtc *crtc,
532 struct drm_atomic_state *crtc_state)
533 {
534 struct bochs_device *bochs = to_bochs_device(crtc->dev);
535
536 bochs_hw_blank(bochs, true);
537 }
538
539 static const struct drm_crtc_helper_funcs bochs_crtc_helper_funcs = {
540 .mode_set_nofb = bochs_crtc_helper_mode_set_nofb,
541 .atomic_check = bochs_crtc_helper_atomic_check,
542 .atomic_enable = bochs_crtc_helper_atomic_enable,
543 .atomic_disable = bochs_crtc_helper_atomic_disable,
544 };
545
546 static const struct drm_crtc_funcs bochs_crtc_funcs = {
547 .reset = drm_atomic_helper_crtc_reset,
548 .destroy = drm_crtc_cleanup,
549 .set_config = drm_atomic_helper_set_config,
550 .page_flip = drm_atomic_helper_page_flip,
551 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
552 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
553 };
554
555 static const struct drm_encoder_funcs bochs_encoder_funcs = {
556 .destroy = drm_encoder_cleanup,
557 };
558
bochs_connector_helper_get_modes(struct drm_connector * connector)559 static int bochs_connector_helper_get_modes(struct drm_connector *connector)
560 {
561 const struct drm_edid *edid;
562 int count;
563
564 edid = bochs_hw_read_edid(connector);
565
566 if (edid) {
567 drm_edid_connector_update(connector, edid);
568 count = drm_edid_connector_add_modes(connector);
569 drm_edid_free(edid);
570 } else {
571 drm_edid_connector_update(connector, NULL);
572 count = drm_add_modes_noedid(connector, 8192, 8192);
573 drm_set_preferred_mode(connector, defx, defy);
574 }
575
576 return count;
577 }
578
579 static const struct drm_connector_helper_funcs bochs_connector_helper_funcs = {
580 .get_modes = bochs_connector_helper_get_modes,
581 };
582
583 static const struct drm_connector_funcs bochs_connector_funcs = {
584 .fill_modes = drm_helper_probe_single_connector_modes,
585 .destroy = drm_connector_cleanup,
586 .reset = drm_atomic_helper_connector_reset,
587 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
588 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
589 };
590
bochs_mode_config_mode_valid(struct drm_device * dev,const struct drm_display_mode * mode)591 static enum drm_mode_status bochs_mode_config_mode_valid(struct drm_device *dev,
592 const struct drm_display_mode *mode)
593 {
594 struct bochs_device *bochs = to_bochs_device(dev);
595 const struct drm_format_info *format = drm_format_info(DRM_FORMAT_XRGB8888);
596 u64 pitch;
597
598 if (drm_WARN_ON(dev, !format))
599 return MODE_ERROR;
600
601 pitch = drm_format_info_min_pitch(format, 0, mode->hdisplay);
602 if (!pitch)
603 return MODE_BAD_WIDTH;
604 if (mode->vdisplay > DIV_ROUND_DOWN_ULL(bochs->fb_size, pitch))
605 return MODE_MEM;
606
607 return MODE_OK;
608 }
609
610 static const struct drm_mode_config_funcs bochs_mode_config_funcs = {
611 .fb_create = drm_gem_fb_create_with_dirty,
612 .mode_valid = bochs_mode_config_mode_valid,
613 .atomic_check = drm_atomic_helper_check,
614 .atomic_commit = drm_atomic_helper_commit,
615 };
616
bochs_kms_init(struct bochs_device * bochs)617 static int bochs_kms_init(struct bochs_device *bochs)
618 {
619 struct drm_device *dev = &bochs->dev;
620 struct drm_plane *primary_plane;
621 struct drm_crtc *crtc;
622 struct drm_connector *connector;
623 struct drm_encoder *encoder;
624 int ret;
625
626 ret = drmm_mode_config_init(dev);
627 if (ret)
628 return ret;
629
630 dev->mode_config.max_width = 8192;
631 dev->mode_config.max_height = 8192;
632
633 dev->mode_config.preferred_depth = 24;
634 dev->mode_config.quirk_addfb_prefer_host_byte_order = true;
635
636 dev->mode_config.funcs = &bochs_mode_config_funcs;
637
638 primary_plane = &bochs->primary_plane;
639 ret = drm_universal_plane_init(dev, primary_plane, 0,
640 &bochs_primary_plane_funcs,
641 bochs_primary_plane_formats,
642 ARRAY_SIZE(bochs_primary_plane_formats),
643 NULL,
644 DRM_PLANE_TYPE_PRIMARY, NULL);
645 if (ret)
646 return ret;
647 drm_plane_helper_add(primary_plane, &bochs_primary_plane_helper_funcs);
648 drm_plane_enable_fb_damage_clips(primary_plane);
649
650 crtc = &bochs->crtc;
651 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL,
652 &bochs_crtc_funcs, NULL);
653 if (ret)
654 return ret;
655 drm_crtc_helper_add(crtc, &bochs_crtc_helper_funcs);
656
657 encoder = &bochs->encoder;
658 ret = drm_encoder_init(dev, encoder, &bochs_encoder_funcs,
659 DRM_MODE_ENCODER_VIRTUAL, NULL);
660 if (ret)
661 return ret;
662 encoder->possible_crtcs = drm_crtc_mask(crtc);
663
664 connector = &bochs->connector;
665 ret = drm_connector_init(dev, connector, &bochs_connector_funcs,
666 DRM_MODE_CONNECTOR_VIRTUAL);
667 if (ret)
668 return ret;
669 drm_connector_helper_add(connector, &bochs_connector_helper_funcs);
670 drm_connector_attach_edid_property(connector);
671 drm_connector_attach_encoder(connector, encoder);
672
673 drm_mode_config_reset(dev);
674
675 return 0;
676 }
677
678 /* ---------------------------------------------------------------------- */
679 /* drm interface */
680
bochs_load(struct bochs_device * bochs)681 static int bochs_load(struct bochs_device *bochs)
682 {
683 int ret;
684
685 ret = bochs_hw_init(bochs);
686 if (ret)
687 return ret;
688
689 ret = bochs_kms_init(bochs);
690 if (ret)
691 return ret;
692
693 return 0;
694 }
695
696 DEFINE_DRM_GEM_FOPS(bochs_fops);
697
698 static const struct drm_driver bochs_driver = {
699 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
700 .fops = &bochs_fops,
701 .name = "bochs-drm",
702 .desc = "bochs dispi vga interface (qemu stdvga)",
703 .major = 1,
704 .minor = 0,
705 DRM_GEM_SHMEM_DRIVER_OPS,
706 DRM_FBDEV_SHMEM_DRIVER_OPS,
707 };
708
709 /* ---------------------------------------------------------------------- */
710 /* pm interface */
711
712 #ifdef CONFIG_PM_SLEEP
bochs_pm_suspend(struct device * dev)713 static int bochs_pm_suspend(struct device *dev)
714 {
715 struct drm_device *drm_dev = dev_get_drvdata(dev);
716
717 return drm_mode_config_helper_suspend(drm_dev);
718 }
719
bochs_pm_resume(struct device * dev)720 static int bochs_pm_resume(struct device *dev)
721 {
722 struct drm_device *drm_dev = dev_get_drvdata(dev);
723
724 return drm_mode_config_helper_resume(drm_dev);
725 }
726 #endif
727
728 static const struct dev_pm_ops bochs_pm_ops = {
729 SET_SYSTEM_SLEEP_PM_OPS(bochs_pm_suspend,
730 bochs_pm_resume)
731 };
732
733 /* ---------------------------------------------------------------------- */
734 /* pci interface */
735
bochs_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)736 static int bochs_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
737 {
738 struct bochs_device *bochs;
739 struct drm_device *dev;
740 int ret;
741
742 ret = aperture_remove_conflicting_pci_devices(pdev, bochs_driver.name);
743 if (ret)
744 return ret;
745
746 bochs = devm_drm_dev_alloc(&pdev->dev, &bochs_driver, struct bochs_device, dev);
747 if (IS_ERR(bochs))
748 return PTR_ERR(bochs);
749 dev = &bochs->dev;
750
751 ret = pcim_enable_device(pdev);
752 if (ret)
753 goto err_free_dev;
754
755 pci_set_drvdata(pdev, dev);
756
757 ret = bochs_load(bochs);
758 if (ret)
759 goto err_free_dev;
760
761 ret = drm_dev_register(dev, 0);
762 if (ret)
763 goto err_free_dev;
764
765 drm_client_setup(dev, NULL);
766
767 return ret;
768
769 err_free_dev:
770 drm_dev_put(dev);
771 return ret;
772 }
773
bochs_pci_remove(struct pci_dev * pdev)774 static void bochs_pci_remove(struct pci_dev *pdev)
775 {
776 struct drm_device *dev = pci_get_drvdata(pdev);
777
778 drm_dev_unplug(dev);
779 drm_atomic_helper_shutdown(dev);
780 }
781
bochs_pci_shutdown(struct pci_dev * pdev)782 static void bochs_pci_shutdown(struct pci_dev *pdev)
783 {
784 drm_atomic_helper_shutdown(pci_get_drvdata(pdev));
785 }
786
787 static const struct pci_device_id bochs_pci_tbl[] = {
788 {
789 .vendor = 0x1234,
790 .device = 0x1111,
791 .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET,
792 .subdevice = PCI_SUBDEVICE_ID_QEMU,
793 .driver_data = BOCHS_QEMU_STDVGA,
794 },
795 {
796 .vendor = 0x1234,
797 .device = 0x1111,
798 .subvendor = PCI_ANY_ID,
799 .subdevice = PCI_ANY_ID,
800 .driver_data = BOCHS_UNKNOWN,
801 },
802 {
803 .vendor = 0x4321,
804 .device = 0x1111,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .driver_data = BOCHS_SIMICS,
808 },
809 { /* end of list */ }
810 };
811
812 static struct pci_driver bochs_pci_driver = {
813 .name = "bochs-drm",
814 .id_table = bochs_pci_tbl,
815 .probe = bochs_pci_probe,
816 .remove = bochs_pci_remove,
817 .shutdown = bochs_pci_shutdown,
818 .driver.pm = &bochs_pm_ops,
819 };
820
821 /* ---------------------------------------------------------------------- */
822 /* module init/exit */
823
824 drm_module_pci_driver_if_modeset(bochs_pci_driver, bochs_modeset);
825
826 MODULE_DEVICE_TABLE(pci, bochs_pci_tbl);
827 MODULE_AUTHOR("Gerd Hoffmann <kraxel@redhat.com>");
828 MODULE_DESCRIPTION("DRM Support for bochs dispi vga interface (qemu stdvga)");
829 MODULE_LICENSE("GPL");
830