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Searched refs:UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h658 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Duvd_3_1_sh_mask.h528 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Duvd_4_2_sh_mask.h532 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Duvd_4_0_sh_mask.h751 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x00000000 macro
H A Duvd_6_0_sh_mask.h566 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Duvd_5_0_sh_mask.h564 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1178 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Dvcn_2_5_sh_mask.h2688 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Dvcn_2_0_0_sh_mask.h2684 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Dvcn_2_6_0_sh_mask.h41 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Dvcn_3_0_0_sh_mask.h3746 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Dvcn_5_0_0_sh_mask.h3690 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Dvcn_4_0_5_sh_mask.h3858 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Dvcn_4_0_3_sh_mask.h4027 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
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