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Searched refs:UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h296 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
H A Duvd_4_2_sh_mask.h296 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
H A Duvd_4_0_sh_mask.h231 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0x0000000e macro
H A Duvd_6_0_sh_mask.h322 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
H A Duvd_5_0_sh_mask.h320 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_sh_mask.h2040 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
H A Dvcn_2_0_0_sh_mask.h1992 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
H A Dvcn_2_6_0_sh_mask.h3711 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
H A Dvcn_3_0_0_sh_mask.h2770 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
H A Dvcn_5_0_0_sh_mask.h3444 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
H A Dvcn_4_0_5_sh_mask.h3754 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
H A Dvcn_4_0_3_sh_mask.h3923 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe macro
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