1 /****************************************************************************\ 2 * 3 * File Name atomfirmware.h 4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5 * 6 * Description header file of general definitions for OS and pre-OS video drivers 7 * 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11 * and associated documentation files (the "Software"), to deal in the Software without restriction, 12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 \****************************************************************************/ 28 29 /*IMPORTANT NOTES 30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33 */ 34 35 #ifndef _ATOMFIRMWARE_H_ 36 #define _ATOMFIRMWARE_H_ 37 38 enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41 }; 42 43 #ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55 #endif 56 57 enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65 }; 66 67 enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79 }; 80 81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82 enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90 }; 91 92 //ucEncoderMode 93 enum atom_encode_mode_def 94 { 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104 }; 105 106 enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112 }; 113 114 enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118 }; 119 120 enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125 }; 126 127 enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133 }; 134 135 enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142 }; 143 144 /* define panel bit per color */ 145 enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152 }; 153 154 //ucVoltageType 155 enum atom_voltage_type 156 { 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178 }; 179 180 enum atom_dgpu_vram_type { 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61, 184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 185 ATOM_DGPU_VRAM_TYPE_HBM3 = 0x80, 186 ATOM_DGPU_VRAM_TYPE_HBM3E = 0x81, 187 }; 188 189 enum atom_dp_vs_preemph_def{ 190 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 191 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 192 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 193 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 194 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 195 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 196 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 197 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 198 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 199 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 200 }; 201 202 #define BIOS_ATOM_PREFIX "ATOMBIOS" 203 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD" 204 #define BIOS_STRING_LENGTH 43 205 206 /* 207 enum atom_string_def{ 208 asic_bus_type_pcie_string = "PCI_EXPRESS", 209 atom_fire_gl_string = "FGL", 210 atom_bios_string = "ATOM" 211 }; 212 */ 213 214 #pragma pack(1) /* BIOS data must use byte alignment*/ 215 216 enum atombios_image_offset{ 217 OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048, 218 OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002, 219 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94, 220 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/ 221 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f, 222 OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e, 223 OFFSET_TO_VBIOS_PART_NUMBER = 0x80, 224 OFFSET_TO_VBIOS_DATE = 0x50, 225 }; 226 227 /**************************************************************************** 228 * Common header for all tables (Data table, Command function). 229 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 230 * And the pointer actually points to this header. 231 ****************************************************************************/ 232 233 struct atom_common_table_header 234 { 235 uint16_t structuresize; 236 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 237 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 238 }; 239 240 /**************************************************************************** 241 * Structure stores the ROM header. 242 ****************************************************************************/ 243 struct atom_rom_header_v2_2 244 { 245 struct atom_common_table_header table_header; 246 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 247 uint16_t bios_segment_address; 248 uint16_t protectedmodeoffset; 249 uint16_t configfilenameoffset; 250 uint16_t crc_block_offset; 251 uint16_t vbios_bootupmessageoffset; 252 uint16_t int10_offset; 253 uint16_t pcibusdevinitcode; 254 uint16_t iobaseaddress; 255 uint16_t subsystem_vendor_id; 256 uint16_t subsystem_id; 257 uint16_t pci_info_offset; 258 uint16_t masterhwfunction_offset; //Offset for SW to get all command function offsets, Don't change the position 259 uint16_t masterdatatable_offset; //Offset for SW to get all data table offsets, Don't change the position 260 uint16_t reserved; 261 uint32_t pspdirtableoffset; 262 }; 263 264 /*==============================hw function portion======================================================================*/ 265 266 267 /**************************************************************************** 268 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 269 * The real functionality of each function is associated with the parameter structure version when defined 270 * For all internal cmd function definitions, please reference to atomstruct.h 271 ****************************************************************************/ 272 struct atom_master_list_of_command_functions_v2_1{ 273 uint16_t asic_init; //Function 274 uint16_t cmd_function1; //used as an internal one 275 uint16_t cmd_function2; //used as an internal one 276 uint16_t cmd_function3; //used as an internal one 277 uint16_t digxencodercontrol; //Function 278 uint16_t cmd_function5; //used as an internal one 279 uint16_t cmd_function6; //used as an internal one 280 uint16_t cmd_function7; //used as an internal one 281 uint16_t cmd_function8; //used as an internal one 282 uint16_t cmd_function9; //used as an internal one 283 uint16_t setengineclock; //Function 284 uint16_t setmemoryclock; //Function 285 uint16_t setpixelclock; //Function 286 uint16_t enabledisppowergating; //Function 287 uint16_t cmd_function14; //used as an internal one 288 uint16_t cmd_function15; //used as an internal one 289 uint16_t cmd_function16; //used as an internal one 290 uint16_t cmd_function17; //used as an internal one 291 uint16_t cmd_function18; //used as an internal one 292 uint16_t cmd_function19; //used as an internal one 293 uint16_t cmd_function20; //used as an internal one 294 uint16_t cmd_function21; //used as an internal one 295 uint16_t cmd_function22; //used as an internal one 296 uint16_t cmd_function23; //used as an internal one 297 uint16_t cmd_function24; //used as an internal one 298 uint16_t cmd_function25; //used as an internal one 299 uint16_t cmd_function26; //used as an internal one 300 uint16_t cmd_function27; //used as an internal one 301 uint16_t cmd_function28; //used as an internal one 302 uint16_t cmd_function29; //used as an internal one 303 uint16_t cmd_function30; //used as an internal one 304 uint16_t cmd_function31; //used as an internal one 305 uint16_t cmd_function32; //used as an internal one 306 uint16_t cmd_function33; //used as an internal one 307 uint16_t blankcrtc; //Function 308 uint16_t enablecrtc; //Function 309 uint16_t cmd_function36; //used as an internal one 310 uint16_t cmd_function37; //used as an internal one 311 uint16_t cmd_function38; //used as an internal one 312 uint16_t cmd_function39; //used as an internal one 313 uint16_t cmd_function40; //used as an internal one 314 uint16_t getsmuclockinfo; //Function 315 uint16_t selectcrtc_source; //Function 316 uint16_t cmd_function43; //used as an internal one 317 uint16_t cmd_function44; //used as an internal one 318 uint16_t cmd_function45; //used as an internal one 319 uint16_t setdceclock; //Function 320 uint16_t getmemoryclock; //Function 321 uint16_t getengineclock; //Function 322 uint16_t setcrtc_usingdtdtiming; //Function 323 uint16_t externalencodercontrol; //Function 324 uint16_t cmd_function51; //used as an internal one 325 uint16_t cmd_function52; //used as an internal one 326 uint16_t cmd_function53; //used as an internal one 327 uint16_t processi2cchanneltransaction;//Function 328 uint16_t cmd_function55; //used as an internal one 329 uint16_t cmd_function56; //used as an internal one 330 uint16_t cmd_function57; //used as an internal one 331 uint16_t cmd_function58; //used as an internal one 332 uint16_t cmd_function59; //used as an internal one 333 uint16_t computegpuclockparam; //Function 334 uint16_t cmd_function61; //used as an internal one 335 uint16_t cmd_function62; //used as an internal one 336 uint16_t dynamicmemorysettings; //Function function 337 uint16_t memorytraining; //Function function 338 uint16_t cmd_function65; //used as an internal one 339 uint16_t cmd_function66; //used as an internal one 340 uint16_t setvoltage; //Function 341 uint16_t cmd_function68; //used as an internal one 342 uint16_t readefusevalue; //Function 343 uint16_t cmd_function70; //used as an internal one 344 uint16_t cmd_function71; //used as an internal one 345 uint16_t cmd_function72; //used as an internal one 346 uint16_t cmd_function73; //used as an internal one 347 uint16_t cmd_function74; //used as an internal one 348 uint16_t cmd_function75; //used as an internal one 349 uint16_t dig1transmittercontrol; //Function 350 uint16_t cmd_function77; //used as an internal one 351 uint16_t processauxchanneltransaction;//Function 352 uint16_t cmd_function79; //used as an internal one 353 uint16_t getvoltageinfo; //Function 354 }; 355 356 struct atom_master_command_function_v2_1 357 { 358 struct atom_common_table_header table_header; 359 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 360 }; 361 362 /**************************************************************************** 363 * Structures used in every command function 364 ****************************************************************************/ 365 struct atom_function_attribute 366 { 367 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 368 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 369 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 370 }; 371 372 373 /**************************************************************************** 374 * Common header for all hw functions. 375 * Every function pointed by _master_list_of_hw_function has this common header. 376 * And the pointer actually points to this header. 377 ****************************************************************************/ 378 struct atom_rom_hw_function_header 379 { 380 struct atom_common_table_header func_header; 381 struct atom_function_attribute func_attrib; 382 }; 383 384 385 /*==============================sw data table portion======================================================================*/ 386 /**************************************************************************** 387 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 388 * The real name of each table is given when its data structure version is defined 389 ****************************************************************************/ 390 struct atom_master_list_of_data_tables_v2_1{ 391 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 392 uint16_t multimedia_info; 393 uint16_t smc_dpm_info; 394 uint16_t sw_datatable3; 395 uint16_t firmwareinfo; /* Shared by various SW components */ 396 uint16_t sw_datatable5; 397 uint16_t lcd_info; /* Shared by various SW components */ 398 uint16_t sw_datatable7; 399 uint16_t smu_info; 400 uint16_t sw_datatable9; 401 uint16_t sw_datatable10; 402 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 403 uint16_t gpio_pin_lut; /* Shared by various SW components */ 404 uint16_t sw_datatable13; 405 uint16_t gfx_info; 406 uint16_t powerplayinfo; /* Shared by various SW components */ 407 uint16_t sw_datatable16; 408 uint16_t sw_datatable17; 409 uint16_t sw_datatable18; 410 uint16_t sw_datatable19; 411 uint16_t sw_datatable20; 412 uint16_t sw_datatable21; 413 uint16_t displayobjectinfo; /* Shared by various SW components */ 414 uint16_t indirectioaccess; /* used as an internal one */ 415 uint16_t umc_info; /* Shared by various SW components */ 416 uint16_t sw_datatable25; 417 uint16_t sw_datatable26; 418 uint16_t dce_info; /* Shared by various SW components */ 419 uint16_t vram_info; /* Shared by various SW components */ 420 uint16_t sw_datatable29; 421 uint16_t integratedsysteminfo; /* Shared by various SW components */ 422 uint16_t asic_profiling_info; /* Shared by various SW components */ 423 uint16_t voltageobject_info; /* shared by various SW components */ 424 uint16_t sw_datatable33; 425 uint16_t sw_datatable34; 426 }; 427 428 429 struct atom_master_data_table_v2_1 430 { 431 struct atom_common_table_header table_header; 432 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 433 }; 434 435 436 struct atom_dtd_format 437 { 438 uint16_t pixclk; 439 uint16_t h_active; 440 uint16_t h_blanking_time; 441 uint16_t v_active; 442 uint16_t v_blanking_time; 443 uint16_t h_sync_offset; 444 uint16_t h_sync_width; 445 uint16_t v_sync_offset; 446 uint16_t v_syncwidth; 447 uint16_t reserved; 448 uint16_t reserved0; 449 uint8_t h_border; 450 uint8_t v_border; 451 uint16_t miscinfo; 452 uint8_t atom_mode_id; 453 uint8_t refreshrate; 454 }; 455 456 /* atom_dtd_format.modemiscinfo definition */ 457 enum atom_dtd_format_modemiscinfo{ 458 ATOM_HSYNC_POLARITY = 0x0002, 459 ATOM_VSYNC_POLARITY = 0x0004, 460 ATOM_H_REPLICATIONBY2 = 0x0010, 461 ATOM_V_REPLICATIONBY2 = 0x0020, 462 ATOM_INTERLACE = 0x0080, 463 ATOM_COMPOSITESYNC = 0x0040, 464 }; 465 466 467 /* utilitypipeline 468 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 469 * the location of it can't change 470 */ 471 472 473 /* 474 *************************************************************************** 475 Data Table firmwareinfo structure 476 *************************************************************************** 477 */ 478 479 struct atom_firmware_info_v3_1 480 { 481 struct atom_common_table_header table_header; 482 uint32_t firmware_revision; 483 uint32_t bootup_sclk_in10khz; 484 uint32_t bootup_mclk_in10khz; 485 uint32_t firmware_capability; // enum atombios_firmware_capability 486 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 487 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 488 uint16_t bootup_vddc_mv; 489 uint16_t bootup_vddci_mv; 490 uint16_t bootup_mvddc_mv; 491 uint16_t bootup_vddgfx_mv; 492 uint8_t mem_module_id; 493 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 494 uint8_t reserved1[2]; 495 uint32_t mc_baseaddr_high; 496 uint32_t mc_baseaddr_low; 497 uint32_t reserved2[6]; 498 }; 499 500 /* Total 32bit cap indication */ 501 enum atombios_firmware_capability 502 { 503 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 504 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 505 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 506 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 507 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 508 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 509 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, 510 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, 511 ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000, 512 }; 513 514 enum atom_cooling_solution_id{ 515 AIR_COOLING = 0x00, 516 LIQUID_COOLING = 0x01 517 }; 518 519 struct atom_firmware_info_v3_2 { 520 struct atom_common_table_header table_header; 521 uint32_t firmware_revision; 522 uint32_t bootup_sclk_in10khz; 523 uint32_t bootup_mclk_in10khz; 524 uint32_t firmware_capability; // enum atombios_firmware_capability 525 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 526 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 527 uint16_t bootup_vddc_mv; 528 uint16_t bootup_vddci_mv; 529 uint16_t bootup_mvddc_mv; 530 uint16_t bootup_vddgfx_mv; 531 uint8_t mem_module_id; 532 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 533 uint8_t reserved1[2]; 534 uint32_t mc_baseaddr_high; 535 uint32_t mc_baseaddr_low; 536 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 537 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 538 uint8_t board_i2c_feature_slave_addr; 539 uint8_t reserved3; 540 uint16_t bootup_mvddq_mv; 541 uint16_t bootup_mvpp_mv; 542 uint32_t zfbstartaddrin16mb; 543 uint32_t reserved2[3]; 544 }; 545 546 struct atom_firmware_info_v3_3 547 { 548 struct atom_common_table_header table_header; 549 uint32_t firmware_revision; 550 uint32_t bootup_sclk_in10khz; 551 uint32_t bootup_mclk_in10khz; 552 uint32_t firmware_capability; // enum atombios_firmware_capability 553 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 554 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 555 uint16_t bootup_vddc_mv; 556 uint16_t bootup_vddci_mv; 557 uint16_t bootup_mvddc_mv; 558 uint16_t bootup_vddgfx_mv; 559 uint8_t mem_module_id; 560 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 561 uint8_t reserved1[2]; 562 uint32_t mc_baseaddr_high; 563 uint32_t mc_baseaddr_low; 564 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 565 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 566 uint8_t board_i2c_feature_slave_addr; 567 uint8_t reserved3; 568 uint16_t bootup_mvddq_mv; 569 uint16_t bootup_mvpp_mv; 570 uint32_t zfbstartaddrin16mb; 571 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 572 uint32_t reserved2[2]; 573 }; 574 575 struct atom_firmware_info_v3_4 { 576 struct atom_common_table_header table_header; 577 uint32_t firmware_revision; 578 uint32_t bootup_sclk_in10khz; 579 uint32_t bootup_mclk_in10khz; 580 uint32_t firmware_capability; // enum atombios_firmware_capability 581 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 582 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 583 uint16_t bootup_vddc_mv; 584 uint16_t bootup_vddci_mv; 585 uint16_t bootup_mvddc_mv; 586 uint16_t bootup_vddgfx_mv; 587 uint8_t mem_module_id; 588 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 589 uint8_t reserved1[2]; 590 uint32_t mc_baseaddr_high; 591 uint32_t mc_baseaddr_low; 592 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 593 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 594 uint8_t board_i2c_feature_slave_addr; 595 uint8_t ras_rom_i2c_slave_addr; 596 uint16_t bootup_mvddq_mv; 597 uint16_t bootup_mvpp_mv; 598 uint32_t zfbstartaddrin16mb; 599 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 600 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2) 601 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap 602 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap 603 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap 604 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap 605 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 606 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 607 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 608 uint32_t pspbl_init_done_reg_addr; 609 uint32_t pspbl_init_done_value; 610 uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done 611 uint32_t reserved[2]; 612 }; 613 614 struct atom_firmware_info_v3_5 { 615 struct atom_common_table_header table_header; 616 uint32_t firmware_revision; 617 uint32_t bootup_clk_reserved[2]; 618 uint32_t firmware_capability; // enum atombios_firmware_capability 619 uint32_t fw_protect_region_size_in_kb; /* FW allocate a write protect region at top of FB. */ 620 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 621 uint32_t bootup_voltage_reserved[2]; 622 uint8_t mem_module_id; 623 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 624 uint8_t hw_blt_mode; //0:HW_BLT_DMA_PIO_MODE; 1:HW_BLT_LITE_SDMA_MODE; 2:HW_BLT_PCI_IO_MODE 625 uint8_t reserved1; 626 uint32_t mc_baseaddr_high; 627 uint32_t mc_baseaddr_low; 628 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 629 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 630 uint8_t board_i2c_feature_slave_addr; 631 uint8_t ras_rom_i2c_slave_addr; 632 uint32_t bootup_voltage_reserved1; 633 uint32_t zfb_reserved; 634 // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 635 uint32_t pplib_pptable_id; 636 uint32_t hw_voltage_reserved[3]; 637 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 638 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 639 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 640 uint32_t pspbl_init_reserved[3]; 641 uint32_t spi_rom_size; // GPU spi rom size 642 uint16_t support_dev_in_objinfo; 643 uint16_t disp_phy_tunning_size; 644 uint32_t reserved[16]; 645 }; 646 /* 647 *************************************************************************** 648 Data Table lcd_info structure 649 *************************************************************************** 650 */ 651 652 struct lcd_info_v2_1 653 { 654 struct atom_common_table_header table_header; 655 struct atom_dtd_format lcd_timing; 656 uint16_t backlight_pwm; 657 uint16_t special_handle_cap; 658 uint16_t panel_misc; 659 uint16_t lvds_max_slink_pclk; 660 uint16_t lvds_ss_percentage; 661 uint16_t lvds_ss_rate_10hz; 662 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 663 uint8_t pwr_on_de_to_vary_bl; 664 uint8_t pwr_down_vary_bloff_to_de; 665 uint8_t pwr_down_de_to_digoff; 666 uint8_t pwr_off_delay; 667 uint8_t pwr_on_vary_bl_to_blon; 668 uint8_t pwr_down_bloff_to_vary_bloff; 669 uint8_t panel_bpc; 670 uint8_t dpcd_edp_config_cap; 671 uint8_t dpcd_max_link_rate; 672 uint8_t dpcd_max_lane_count; 673 uint8_t dpcd_max_downspread; 674 uint8_t min_allowed_bl_level; 675 uint8_t max_allowed_bl_level; 676 uint8_t bootup_bl_level; 677 uint8_t dplvdsrxid; 678 uint32_t reserved1[8]; 679 }; 680 681 /* lcd_info_v2_1.panel_misc definition */ 682 enum atom_lcd_info_panel_misc{ 683 ATOM_PANEL_MISC_FPDI =0x0002, 684 }; 685 686 //uceDPToLVDSRxId 687 enum atom_lcd_info_dptolvds_rx_id 688 { 689 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 690 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 691 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 692 }; 693 694 695 /* 696 *************************************************************************** 697 Data Table gpio_pin_lut structure 698 *************************************************************************** 699 */ 700 701 struct atom_gpio_pin_assignment 702 { 703 uint32_t data_a_reg_index; 704 uint8_t gpio_bitshift; 705 uint8_t gpio_mask_bitshift; 706 uint8_t gpio_id; 707 uint8_t reserved; 708 }; 709 710 /* atom_gpio_pin_assignment.gpio_id definition */ 711 enum atom_gpio_pin_assignment_gpio_id { 712 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 713 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 714 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 715 716 /* gpio_id pre-define id for multiple usage */ 717 /* GPIO use to control PCIE_VDDC in certain SLT board */ 718 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 719 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC switching feature is enable */ 720 PP_AC_DC_SWITCH_GPIO_PINID = 60, 721 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 722 VDDC_VRHOT_GPIO_PINID = 61, 723 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 724 VDDC_PCC_GPIO_PINID = 62, 725 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 726 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 727 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 728 DRAM_SELF_REFRESH_GPIO_PINID = 64, 729 /* Thermal interrupt output->system thermal chip GPIO pin */ 730 THERMAL_INT_OUTPUT_GPIO_PINID =65, 731 }; 732 733 734 struct atom_gpio_pin_lut_v2_1 735 { 736 struct atom_common_table_header table_header; 737 /*the real number of this included in the structure is calculated by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 738 struct atom_gpio_pin_assignment gpio_pin[]; 739 }; 740 741 742 /* 743 * VBIOS/PRE-OS always reserve a FB region at the top of frame buffer. driver should not write 744 * access that region. driver can allocate their own reservation region as long as it does not 745 * overlap firwmare's reservation region. 746 * if (pre-NV1X) atom data table firmwareInfoTable version < 3.3: 747 * in this case, atom data table vram_usagebyfirmwareTable version always <= 2.1 748 * if VBIOS/UEFI GOP is posted: 749 * VBIOS/UEFIGOP update used_by_firmware_in_kb = total reserved size by VBIOS 750 * update start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb; 751 * ( total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10) 752 * driver can allocate driver reservation region under firmware reservation, 753 * used_by_driver_in_kb = driver reservation size 754 * driver reservation start address = (start_address_in_kb - used_by_driver_in_kb) 755 * Comment1[hchan]: There is only one reservation at the beginning of the FB reserved by 756 * host driver. Host driver would overwrite the table with the following 757 * used_by_firmware_in_kb = total reserved size for pf-vf info exchange and 758 * set SRIOV_MSG_SHARE_RESERVATION mask start_address_in_kb = 0 759 * else there is no VBIOS reservation region: 760 * driver must allocate driver reservation region at top of FB. 761 * driver set used_by_driver_in_kb = driver reservation size 762 * driver reservation start address = (total_mem_size_in_kb - used_by_driver_in_kb) 763 * same as Comment1 764 * else (NV1X and after): 765 * if VBIOS/UEFI GOP is posted: 766 * VBIOS/UEFIGOP update: 767 * used_by_firmware_in_kb = atom_firmware_Info_v3_3.fw_reserved_size_in_kb; 768 * start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb; 769 * (total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10) 770 * if vram_usagebyfirmwareTable version <= 2.1: 771 * driver can allocate driver reservation region under firmware reservation, 772 * driver set used_by_driver_in_kb = driver reservation size 773 * driver reservation start address = start_address_in_kb - used_by_driver_in_kb 774 * same as Comment1 775 * else driver can: 776 * allocate it reservation any place as long as it does overlap pre-OS FW reservation area 777 * set used_by_driver_region0_in_kb = driver reservation size 778 * set driver_region0_start_address_in_kb = driver reservation region start address 779 * Comment2[hchan]: Host driver can set used_by_firmware_in_kb and start_address_in_kb to 780 * zero as the reservation for VF as it doesn’t exist. And Host driver should also 781 * update atom_firmware_Info table to remove the same VBIOS reservation as well. 782 */ 783 784 struct vram_usagebyfirmware_v2_1 785 { 786 struct atom_common_table_header table_header; 787 uint32_t start_address_in_kb; 788 uint16_t used_by_firmware_in_kb; 789 uint16_t used_by_driver_in_kb; 790 }; 791 792 struct vram_usagebyfirmware_v2_2 { 793 struct atom_common_table_header table_header; 794 uint32_t fw_region_start_address_in_kb; 795 uint16_t used_by_firmware_in_kb; 796 uint16_t reserved; 797 uint32_t driver_region0_start_address_in_kb; 798 uint32_t used_by_driver_region0_in_kb; 799 uint32_t reserved32[7]; 800 }; 801 802 /* 803 *************************************************************************** 804 Data Table displayobjectinfo structure 805 *************************************************************************** 806 */ 807 808 enum atom_object_record_type_id { 809 ATOM_I2C_RECORD_TYPE = 1, 810 ATOM_HPD_INT_RECORD_TYPE = 2, 811 ATOM_CONNECTOR_CAP_RECORD_TYPE = 3, 812 ATOM_CONNECTOR_SPEED_UPTO = 4, 813 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE = 9, 814 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE = 16, 815 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE = 17, 816 ATOM_ENCODER_CAP_RECORD_TYPE = 20, 817 ATOM_BRACKET_LAYOUT_RECORD_TYPE = 21, 818 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE = 22, 819 ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE = 23, 820 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE = 25, 821 ATOM_RECORD_END_TYPE = 0xFF, 822 }; 823 824 struct atom_common_record_header 825 { 826 uint8_t record_type; //An emun to indicate the record type 827 uint8_t record_size; //The size of the whole record in byte 828 }; 829 830 struct atom_i2c_record 831 { 832 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 833 uint8_t i2c_id; 834 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 835 }; 836 837 struct atom_hpd_int_record 838 { 839 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 840 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 841 uint8_t plugin_pin_state; 842 }; 843 844 struct atom_connector_caps_record { 845 struct atom_common_record_header 846 record_header; //record_type = ATOM_CONN_CAP_RECORD_TYPE 847 uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of Not 848 }; 849 850 struct atom_connector_speed_record { 851 struct atom_common_record_header 852 record_header; //record_type = ATOM_CONN_SPEED_UPTO 853 uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz. 854 uint16_t reserved; 855 }; 856 857 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 858 enum atom_encoder_caps_def 859 { 860 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 861 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 862 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 863 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 864 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 865 ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board. 866 ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board 867 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board 868 ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported by board 869 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 870 }; 871 872 struct atom_encoder_caps_record 873 { 874 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 875 uint32_t encodercaps; 876 }; 877 878 enum atom_connector_caps_def 879 { 880 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 881 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 882 ATOM_CONNECTOR_CAP_DP_PLUS_PLUS_TYPE2_ONLY = 0x10, //a cap bit that indicates connector with DP_PLUS_PLUS_TYPE2_ONLY 883 }; 884 885 struct atom_disp_connector_caps_record 886 { 887 struct atom_common_record_header record_header; 888 uint32_t connectcaps; 889 }; 890 891 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 892 struct atom_gpio_pin_control_pair 893 { 894 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 895 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 896 }; 897 898 struct atom_object_gpio_cntl_record 899 { 900 struct atom_common_record_header record_header; 901 uint8_t flag; // Future expnadibility 902 uint8_t number_of_pins; // Number of GPIO pins used to control the object 903 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 904 }; 905 906 //Definitions for GPIO pin state 907 enum atom_gpio_pin_control_pinstate_def 908 { 909 GPIO_PIN_TYPE_INPUT = 0x00, 910 GPIO_PIN_TYPE_OUTPUT = 0x10, 911 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 912 913 //For GPIO_PIN_TYPE_OUTPUT the following is defined 914 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 915 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 916 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 917 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 918 }; 919 920 // Indexes to GPIO array in GLSync record 921 // GLSync record is for Frame Lock/Gen Lock feature. 922 enum atom_glsync_record_gpio_index_def 923 { 924 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 925 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 926 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 927 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 928 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 929 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 930 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 931 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 932 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 933 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 934 }; 935 936 937 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 938 { 939 struct atom_common_record_header record_header; 940 uint8_t hpd_pin_map[8]; 941 }; 942 943 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 944 { 945 struct atom_common_record_header record_header; 946 uint8_t aux_ddc_map[8]; 947 }; 948 949 struct atom_connector_forced_tmds_cap_record 950 { 951 struct atom_common_record_header record_header; 952 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 953 uint8_t maxtmdsclkrate_in2_5mhz; 954 uint8_t reserved; 955 }; 956 957 struct atom_connector_layout_info 958 { 959 uint16_t connectorobjid; 960 uint8_t connector_type; 961 uint8_t position; 962 }; 963 964 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 965 enum atom_connector_layout_info_connector_type_def 966 { 967 CONNECTOR_TYPE_DVI_D = 1, 968 969 CONNECTOR_TYPE_HDMI = 4, 970 CONNECTOR_TYPE_DISPLAY_PORT = 5, 971 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 972 }; 973 974 struct atom_bracket_layout_record 975 { 976 struct atom_common_record_header record_header; 977 uint8_t bracketlen; 978 uint8_t bracketwidth; 979 uint8_t conn_num; 980 uint8_t reserved; 981 struct atom_connector_layout_info conn_info[1]; 982 }; 983 struct atom_bracket_layout_record_v2 { 984 struct atom_common_record_header 985 record_header; //record_type = ATOM_BRACKET_LAYOUT_RECORD_TYPE 986 uint8_t bracketlen; //Bracket Length in mm 987 uint8_t bracketwidth; //Bracket Width in mm 988 uint8_t conn_num; //Connector numbering 989 uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini) 990 uint8_t reserved1; 991 uint8_t reserved2; 992 }; 993 994 enum atom_connector_layout_info_mini_type_def { 995 MINI_TYPE_NORMAL = 0, 996 MINI_TYPE_MINI = 1, 997 }; 998 999 enum atom_display_device_tag_def{ 1000 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 1001 ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compatibility 1002 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 1003 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 1004 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 1005 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 1006 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 1007 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 1008 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 1009 }; 1010 1011 struct atom_display_object_path_v2 1012 { 1013 uint16_t display_objid; //Connector Object ID or Misc Object ID 1014 uint16_t disp_recordoffset; 1015 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or internal encoder 1016 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 1017 uint16_t encoder_recordoffset; 1018 uint16_t extencoder_recordoffset; 1019 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 1020 uint8_t priority_id; 1021 uint8_t reserved; 1022 }; 1023 1024 struct atom_display_object_path_v3 { 1025 uint16_t display_objid; //Connector Object ID or Misc Object ID 1026 uint16_t disp_recordoffset; 1027 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or internal encoder 1028 uint16_t reserved1; //only on USBC case, otherwise always = 0 1029 uint16_t reserved2; //reserved and always = 0 1030 uint16_t reserved3; //reserved and always = 0 1031 //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, 1032 //a path appears first 1033 uint16_t device_tag; 1034 uint16_t reserved4; //reserved and always = 0 1035 }; 1036 1037 struct display_object_info_table_v1_4 1038 { 1039 struct atom_common_table_header table_header; 1040 uint16_t supporteddevices; 1041 uint8_t number_of_path; 1042 uint8_t reserved; 1043 struct atom_display_object_path_v2 display_path[]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 1044 }; 1045 1046 struct display_object_info_table_v1_5 { 1047 struct atom_common_table_header table_header; 1048 uint16_t supporteddevices; 1049 uint8_t number_of_path; 1050 uint8_t reserved; 1051 // the real number of this included in the structure is calculated by using the 1052 // (whole structure size - the header size- number_of_path)/size of atom_display_object_path 1053 struct atom_display_object_path_v3 display_path[]; 1054 }; 1055 1056 /* 1057 *************************************************************************** 1058 Data Table dce_info structure 1059 *************************************************************************** 1060 */ 1061 struct atom_display_controller_info_v4_1 1062 { 1063 struct atom_common_table_header table_header; 1064 uint32_t display_caps; 1065 uint32_t bootup_dispclk_10khz; 1066 uint16_t dce_refclk_10khz; 1067 uint16_t i2c_engine_refclk_10khz; 1068 uint16_t dvi_ss_percentage; // in unit of 0.001% 1069 uint16_t dvi_ss_rate_10hz; 1070 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1071 uint16_t hdmi_ss_rate_10hz; 1072 uint16_t dp_ss_percentage; // in unit of 0.001% 1073 uint16_t dp_ss_rate_10hz; 1074 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1075 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1076 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1077 uint8_t ss_reserved; 1078 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 1079 uint8_t reserved1[3]; 1080 uint16_t dpphy_refclk_10khz; 1081 uint16_t reserved2; 1082 uint8_t dceip_min_ver; 1083 uint8_t dceip_max_ver; 1084 uint8_t max_disp_pipe_num; 1085 uint8_t max_vbios_active_disp_pipe_num; 1086 uint8_t max_ppll_num; 1087 uint8_t max_disp_phy_num; 1088 uint8_t max_aux_pairs; 1089 uint8_t remotedisplayconfig; 1090 uint8_t reserved3[8]; 1091 }; 1092 1093 struct atom_display_controller_info_v4_2 1094 { 1095 struct atom_common_table_header table_header; 1096 uint32_t display_caps; 1097 uint32_t bootup_dispclk_10khz; 1098 uint16_t dce_refclk_10khz; 1099 uint16_t i2c_engine_refclk_10khz; 1100 uint16_t dvi_ss_percentage; // in unit of 0.001% 1101 uint16_t dvi_ss_rate_10hz; 1102 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1103 uint16_t hdmi_ss_rate_10hz; 1104 uint16_t dp_ss_percentage; // in unit of 0.001% 1105 uint16_t dp_ss_rate_10hz; 1106 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1107 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1108 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1109 uint8_t ss_reserved; 1110 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1111 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1112 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1113 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1114 uint16_t dpphy_refclk_10khz; 1115 uint16_t reserved2; 1116 uint8_t dcnip_min_ver; 1117 uint8_t dcnip_max_ver; 1118 uint8_t max_disp_pipe_num; 1119 uint8_t max_vbios_active_disp_pipe_num; 1120 uint8_t max_ppll_num; 1121 uint8_t max_disp_phy_num; 1122 uint8_t max_aux_pairs; 1123 uint8_t remotedisplayconfig; 1124 uint8_t reserved3[8]; 1125 }; 1126 1127 struct atom_display_controller_info_v4_3 1128 { 1129 struct atom_common_table_header table_header; 1130 uint32_t display_caps; 1131 uint32_t bootup_dispclk_10khz; 1132 uint16_t dce_refclk_10khz; 1133 uint16_t i2c_engine_refclk_10khz; 1134 uint16_t dvi_ss_percentage; // in unit of 0.001% 1135 uint16_t dvi_ss_rate_10hz; 1136 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1137 uint16_t hdmi_ss_rate_10hz; 1138 uint16_t dp_ss_percentage; // in unit of 0.001% 1139 uint16_t dp_ss_rate_10hz; 1140 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1141 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1142 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1143 uint8_t ss_reserved; 1144 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1145 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1146 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1147 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1148 uint16_t dpphy_refclk_10khz; 1149 uint16_t reserved2; 1150 uint8_t dcnip_min_ver; 1151 uint8_t dcnip_max_ver; 1152 uint8_t max_disp_pipe_num; 1153 uint8_t max_vbios_active_disp_pipe_num; 1154 uint8_t max_ppll_num; 1155 uint8_t max_disp_phy_num; 1156 uint8_t max_aux_pairs; 1157 uint8_t remotedisplayconfig; 1158 uint8_t reserved3[8]; 1159 }; 1160 1161 struct atom_display_controller_info_v4_4 { 1162 struct atom_common_table_header table_header; 1163 uint32_t display_caps; 1164 uint32_t bootup_dispclk_10khz; 1165 uint16_t dce_refclk_10khz; 1166 uint16_t i2c_engine_refclk_10khz; 1167 uint16_t dvi_ss_percentage; // in unit of 0.001% 1168 uint16_t dvi_ss_rate_10hz; 1169 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1170 uint16_t hdmi_ss_rate_10hz; 1171 uint16_t dp_ss_percentage; // in unit of 0.001% 1172 uint16_t dp_ss_rate_10hz; 1173 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1174 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1175 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1176 uint8_t ss_reserved; 1177 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1178 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1179 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1180 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1181 uint16_t dpphy_refclk_10khz; 1182 uint16_t hw_chip_id; 1183 uint8_t dcnip_min_ver; 1184 uint8_t dcnip_max_ver; 1185 uint8_t max_disp_pipe_num; 1186 uint8_t max_vbios_active_disp_pipum; 1187 uint8_t max_ppll_num; 1188 uint8_t max_disp_phy_num; 1189 uint8_t max_aux_pairs; 1190 uint8_t remotedisplayconfig; 1191 uint32_t dispclk_pll_vco_freq; 1192 uint32_t dp_ref_clk_freq; 1193 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1194 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1195 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1196 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1197 uint16_t dc_golden_table_ver; 1198 uint32_t reserved3[3]; 1199 }; 1200 1201 struct atom_dc_golden_table_v1 1202 { 1203 uint32_t aux_dphy_rx_control0_val; 1204 uint32_t aux_dphy_tx_control_val; 1205 uint32_t aux_dphy_rx_control1_val; 1206 uint32_t dc_gpio_aux_ctrl_0_val; 1207 uint32_t dc_gpio_aux_ctrl_1_val; 1208 uint32_t dc_gpio_aux_ctrl_2_val; 1209 uint32_t dc_gpio_aux_ctrl_3_val; 1210 uint32_t dc_gpio_aux_ctrl_4_val; 1211 uint32_t dc_gpio_aux_ctrl_5_val; 1212 uint32_t reserved[23]; 1213 }; 1214 1215 enum dce_info_caps_def { 1216 // only for VBIOS 1217 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02, 1218 // only for VBIOS 1219 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04, 1220 // only for VBIOS 1221 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08, 1222 // only for VBIOS 1223 DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20, 1224 DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, 1225 }; 1226 1227 struct atom_display_controller_info_v4_5 1228 { 1229 struct atom_common_table_header table_header; 1230 uint32_t display_caps; 1231 uint32_t bootup_dispclk_10khz; 1232 uint16_t dce_refclk_10khz; 1233 uint16_t i2c_engine_refclk_10khz; 1234 uint16_t dvi_ss_percentage; // in unit of 0.001% 1235 uint16_t dvi_ss_rate_10hz; 1236 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1237 uint16_t hdmi_ss_rate_10hz; 1238 uint16_t dp_ss_percentage; // in unit of 0.001% 1239 uint16_t dp_ss_rate_10hz; 1240 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1241 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1242 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1243 uint8_t ss_reserved; 1244 // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1245 uint8_t dfp_hardcode_mode_num; 1246 // DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1247 uint8_t dfp_hardcode_refreshrate; 1248 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1249 uint8_t vga_hardcode_mode_num; 1250 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1251 uint8_t vga_hardcode_refreshrate; 1252 uint16_t dpphy_refclk_10khz; 1253 uint16_t hw_chip_id; 1254 uint8_t dcnip_min_ver; 1255 uint8_t dcnip_max_ver; 1256 uint8_t max_disp_pipe_num; 1257 uint8_t max_vbios_active_disp_pipe_num; 1258 uint8_t max_ppll_num; 1259 uint8_t max_disp_phy_num; 1260 uint8_t max_aux_pairs; 1261 uint8_t remotedisplayconfig; 1262 uint32_t dispclk_pll_vco_freq; 1263 uint32_t dp_ref_clk_freq; 1264 // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1265 uint32_t max_mclk_chg_lat; 1266 // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1267 uint32_t max_sr_exit_lat; 1268 // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1269 uint32_t max_sr_enter_exit_lat; 1270 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1271 uint16_t dc_golden_table_ver; 1272 uint32_t aux_dphy_rx_control0_val; 1273 uint32_t aux_dphy_tx_control_val; 1274 uint32_t aux_dphy_rx_control1_val; 1275 uint32_t dc_gpio_aux_ctrl_0_val; 1276 uint32_t dc_gpio_aux_ctrl_1_val; 1277 uint32_t dc_gpio_aux_ctrl_2_val; 1278 uint32_t dc_gpio_aux_ctrl_3_val; 1279 uint32_t dc_gpio_aux_ctrl_4_val; 1280 uint32_t dc_gpio_aux_ctrl_5_val; 1281 uint32_t reserved[26]; 1282 }; 1283 1284 /* 1285 *************************************************************************** 1286 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 1287 *************************************************************************** 1288 */ 1289 struct atom_ext_display_path 1290 { 1291 uint16_t device_tag; //A bit vector to show what devices are supported 1292 uint16_t device_acpi_enum; //16bit device ACPI id. 1293 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 1294 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 1295 uint8_t hpdlut_index; //An index into external HPD pin LUT 1296 uint16_t ext_encoder_objid; //external encoder object id 1297 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 1298 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 1299 uint16_t caps; 1300 uint16_t reserved; 1301 }; 1302 1303 //usCaps 1304 enum ext_display_path_cap_def { 1305 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007E, 1306 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007E, 1307 AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = (0x01 << 1), 1308 AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x02 << 1), 1309 AMD_EXT_DISPLAY_PATH_CAPS__DP_EARLY_8B10B_TPS2 = (0x03 << 1), 1310 AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x04 << 1), 1311 AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x06 << 1), 1312 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = (0x07 << 1), 1313 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x08 << 1), //PI redriver chip 1314 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x09 << 1), //TI retimer chip 1315 EXT_DISPLAY_PATH_CAPS__AMD_INTERNAL = (0x0a << 1), //AMD internal customer chip placeholder 1316 }; 1317 1318 struct atom_external_display_connection_info 1319 { 1320 struct atom_common_table_header table_header; 1321 uint8_t guid[16]; // a GUID is a 16 byte long string 1322 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 1323 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 1324 uint8_t stereopinid; // use for eDP panel 1325 uint8_t remotedisplayconfig; 1326 uint8_t edptolvdsrxid; 1327 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 1328 uint8_t reserved[3]; // for potential expansion 1329 }; 1330 1331 /* 1332 *************************************************************************** 1333 Data Table integratedsysteminfo structure 1334 *************************************************************************** 1335 */ 1336 1337 struct atom_camera_dphy_timing_param 1338 { 1339 uint8_t profile_id; // SENSOR_PROFILES 1340 uint32_t param; 1341 }; 1342 1343 struct atom_camera_dphy_elec_param 1344 { 1345 uint16_t param[3]; 1346 }; 1347 1348 struct atom_camera_module_info 1349 { 1350 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1351 uint8_t module_name[8]; 1352 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1353 }; 1354 1355 struct atom_camera_flashlight_info 1356 { 1357 uint8_t flashlight_id; // 0: Rear, 1: Front 1358 uint8_t name[8]; 1359 }; 1360 1361 struct atom_camera_data 1362 { 1363 uint32_t versionCode; 1364 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1365 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1366 struct atom_camera_dphy_elec_param dphy_param; 1367 uint32_t crc_val; // CRC 1368 }; 1369 1370 1371 struct atom_14nm_dpphy_dvihdmi_tuningset 1372 { 1373 uint32_t max_symclk_in10khz; 1374 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1375 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1376 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1377 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1378 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1379 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1380 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1381 }; 1382 1383 struct atom_14nm_dpphy_dp_setting{ 1384 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1385 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1386 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1387 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1388 }; 1389 1390 struct atom_14nm_dpphy_dp_tuningset{ 1391 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1392 uint8_t version; 1393 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1394 uint16_t reserved; 1395 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1396 }; 1397 1398 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1399 struct atom_common_table_header table_header; 1400 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1401 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1402 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1403 }; 1404 1405 struct atom_14nm_combphy_tmds_vs_set 1406 { 1407 uint8_t sym_clk; 1408 uint8_t dig_mode; 1409 uint8_t phy_sel; 1410 uint16_t common_mar_deemph_nom__margin_deemph_val; 1411 uint8_t common_seldeemph60__deemph_6db_4_val; 1412 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1413 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1414 uint8_t margin_deemph_lane0__deemph_sel_val; 1415 }; 1416 1417 struct atom_DCN_dpphy_dvihdmi_tuningset 1418 { 1419 uint32_t max_symclk_in10khz; 1420 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1421 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1422 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1423 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1424 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1425 uint8_t reserved1; 1426 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1427 uint8_t reserved2; 1428 }; 1429 1430 struct atom_DCN_dpphy_dp_setting{ 1431 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1432 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1433 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1434 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1435 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1436 }; 1437 1438 struct atom_DCN_dpphy_dp_tuningset{ 1439 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1440 uint8_t version; 1441 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting 1442 uint16_t reserved; 1443 struct atom_DCN_dpphy_dp_setting dptunings[10]; 1444 }; 1445 1446 struct atom_i2c_reg_info { 1447 uint8_t ucI2cRegIndex; 1448 uint8_t ucI2cRegVal; 1449 }; 1450 1451 struct atom_hdmi_retimer_redriver_set { 1452 uint8_t HdmiSlvAddr; 1453 uint8_t HdmiRegNum; 1454 uint8_t Hdmi6GRegNum; 1455 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1456 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1457 }; 1458 1459 struct atom_integrated_system_info_v1_11 1460 { 1461 struct atom_common_table_header table_header; 1462 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1463 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1464 uint32_t system_config; 1465 uint32_t cpucapinfo; 1466 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1467 uint16_t gpuclk_ss_type; 1468 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1469 uint16_t lvds_ss_rate_10hz; 1470 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1471 uint16_t hdmi_ss_rate_10hz; 1472 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1473 uint16_t dvi_ss_rate_10hz; 1474 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1475 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1476 uint16_t backlight_pwm_hz; // pwm frequency in hz 1477 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1478 uint8_t umachannelnumber; // number of memory channels 1479 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1480 uint8_t pwr_on_de_to_vary_bl; 1481 uint8_t pwr_down_vary_bloff_to_de; 1482 uint8_t pwr_down_de_to_digoff; 1483 uint8_t pwr_off_delay; 1484 uint8_t pwr_on_vary_bl_to_blon; 1485 uint8_t pwr_down_bloff_to_vary_bloff; 1486 uint8_t min_allowed_bl_level; 1487 uint8_t htc_hyst_limit; 1488 uint8_t htc_tmp_limit; 1489 uint8_t reserved1; 1490 uint8_t reserved2; 1491 struct atom_external_display_connection_info extdispconninfo; 1492 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1493 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1494 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1495 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1496 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1497 struct atom_camera_data camera_info; 1498 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1499 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1500 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1501 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1502 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1503 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1504 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1505 uint32_t reserved[66]; 1506 }; 1507 1508 struct atom_integrated_system_info_v1_12 1509 { 1510 struct atom_common_table_header table_header; 1511 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1512 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1513 uint32_t system_config; 1514 uint32_t cpucapinfo; 1515 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1516 uint16_t gpuclk_ss_type; 1517 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1518 uint16_t lvds_ss_rate_10hz; 1519 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1520 uint16_t hdmi_ss_rate_10hz; 1521 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1522 uint16_t dvi_ss_rate_10hz; 1523 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1524 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1525 uint16_t backlight_pwm_hz; // pwm frequency in hz 1526 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1527 uint8_t umachannelnumber; // number of memory channels 1528 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms // 1529 uint8_t pwr_on_de_to_vary_bl; 1530 uint8_t pwr_down_vary_bloff_to_de; 1531 uint8_t pwr_down_de_to_digoff; 1532 uint8_t pwr_off_delay; 1533 uint8_t pwr_on_vary_bl_to_blon; 1534 uint8_t pwr_down_bloff_to_vary_bloff; 1535 uint8_t min_allowed_bl_level; 1536 uint8_t htc_hyst_limit; 1537 uint8_t htc_tmp_limit; 1538 uint8_t reserved1; 1539 uint8_t reserved2; 1540 struct atom_external_display_connection_info extdispconninfo; 1541 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1542 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; 1543 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1544 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1545 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1546 struct atom_camera_data camera_info; 1547 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1548 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1549 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1550 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1551 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1552 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1553 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1554 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1555 uint32_t reserved[63]; 1556 }; 1557 1558 struct edp_info_table 1559 { 1560 uint16_t edp_backlight_pwm_hz; 1561 uint16_t edp_ss_percentage; 1562 uint16_t edp_ss_rate_10hz; 1563 uint16_t reserved1; 1564 uint32_t reserved2; 1565 uint8_t edp_pwr_on_off_delay; 1566 uint8_t edp_pwr_on_vary_bl_to_blon; 1567 uint8_t edp_pwr_down_bloff_to_vary_bloff; 1568 uint8_t edp_panel_bpc; 1569 uint8_t edp_bootup_bl_level; 1570 uint8_t reserved3[3]; 1571 uint32_t reserved4[3]; 1572 }; 1573 1574 struct atom_integrated_system_info_v2_1 1575 { 1576 struct atom_common_table_header table_header; 1577 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1578 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1579 uint32_t system_config; 1580 uint32_t cpucapinfo; 1581 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1582 uint16_t gpuclk_ss_type; 1583 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1584 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1585 uint8_t umachannelnumber; // number of memory channels 1586 uint8_t htc_hyst_limit; 1587 uint8_t htc_tmp_limit; 1588 uint8_t reserved1; 1589 uint8_t reserved2; 1590 struct edp_info_table edp1_info; 1591 struct edp_info_table edp2_info; 1592 uint32_t reserved3[8]; 1593 struct atom_external_display_connection_info extdispconninfo; 1594 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1595 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6 1596 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1597 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1598 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset) 1599 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1600 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1601 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1602 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1603 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1604 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset) 1605 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1606 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1607 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1608 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1609 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info 1610 uint32_t reserved7[32]; 1611 1612 }; 1613 1614 struct atom_n6_display_phy_tuning_set { 1615 uint8_t display_signal_type; 1616 uint8_t phy_sel; 1617 uint8_t preset_level; 1618 uint8_t reserved1; 1619 uint32_t reserved2; 1620 uint32_t speed_upto; 1621 uint8_t tx_vboost_level; 1622 uint8_t tx_vreg_v2i; 1623 uint8_t tx_vregdrv_byp; 1624 uint8_t tx_term_cntl; 1625 uint8_t tx_peak_level; 1626 uint8_t tx_slew_en; 1627 uint8_t tx_eq_pre; 1628 uint8_t tx_eq_main; 1629 uint8_t tx_eq_post; 1630 uint8_t tx_en_inv_pre; 1631 uint8_t tx_en_inv_post; 1632 uint8_t reserved3; 1633 uint32_t reserved4; 1634 uint32_t reserved5; 1635 uint32_t reserved6; 1636 }; 1637 1638 struct atom_display_phy_tuning_info { 1639 struct atom_common_table_header table_header; 1640 struct atom_n6_display_phy_tuning_set disp_phy_tuning[1]; 1641 }; 1642 1643 struct atom_integrated_system_info_v2_2 1644 { 1645 struct atom_common_table_header table_header; 1646 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1647 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1648 uint32_t system_config; 1649 uint32_t cpucapinfo; 1650 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1651 uint16_t gpuclk_ss_type; 1652 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1653 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1654 uint8_t umachannelnumber; // number of memory channels 1655 uint8_t htc_hyst_limit; 1656 uint8_t htc_tmp_limit; 1657 uint8_t reserved1; 1658 uint8_t reserved2; 1659 struct edp_info_table edp1_info; 1660 struct edp_info_table edp2_info; 1661 uint32_t reserved3[8]; 1662 struct atom_external_display_connection_info extdispconninfo; 1663 1664 uint32_t reserved4[189]; 1665 }; 1666 1667 struct uma_carveout_option { 1668 char optionName[29]; //max length of string is 28chars + '\0'. Current design is for "minimum", "Medium", "High". This makes entire struct size 64bits 1669 uint8_t memoryCarvedGb; //memory carved out with setting 1670 uint8_t memoryRemainingGb; //memory remaining on system 1671 union { 1672 struct _flags { 1673 uint8_t Auto : 1; 1674 uint8_t Custom : 1; 1675 uint8_t Reserved : 6; 1676 } flags; 1677 uint8_t all8; 1678 } uma_carveout_option_flags; 1679 }; 1680 1681 struct atom_integrated_system_info_v2_3 { 1682 struct atom_common_table_header table_header; 1683 uint32_t vbios_misc; // enum of atom_system_vbiosmisc_def 1684 uint32_t gpucapinfo; // enum of atom_system_gpucapinf_def 1685 uint32_t system_config; 1686 uint32_t cpucapinfo; 1687 uint16_t gpuclk_ss_percentage; // unit of 0.001%, 1000 mean 1% 1688 uint16_t gpuclk_ss_type; 1689 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1690 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1691 uint8_t umachannelnumber; // number of memory channels 1692 uint8_t htc_hyst_limit; 1693 uint8_t htc_tmp_limit; 1694 uint8_t reserved1; // dp_ss_control 1695 uint8_t gpu_package_id; 1696 struct edp_info_table edp1_info; 1697 struct edp_info_table edp2_info; 1698 uint32_t cpuid; 1699 uint32_t vram_bit_width; 1700 uint32_t reserved2[6]; 1701 struct atom_external_display_connection_info extdispconninfo; 1702 uint8_t UMACarveoutVersion; 1703 uint8_t UMACarveoutIndexMax; 1704 uint8_t UMACarveoutTypeDefault; 1705 uint8_t UMACarveoutIndexDefault; 1706 uint8_t UMACarveoutType; //Auto or Custom 1707 uint8_t UMACarveoutIndex; 1708 struct uma_carveout_option UMASizeControlOption[20]; 1709 uint8_t reserved3[110]; 1710 }; 1711 1712 // system_config 1713 enum atom_system_vbiosmisc_def{ 1714 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1715 }; 1716 1717 1718 // gpucapinfo 1719 enum atom_system_gpucapinf_def{ 1720 SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS = 0x10, 1721 }; 1722 1723 //dpphy_override 1724 enum atom_sysinfo_dpphy_override_def{ 1725 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1726 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1727 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1728 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1729 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1730 }; 1731 1732 //lvds_misc 1733 enum atom_sys_info_lvds_misc_def 1734 { 1735 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1736 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1737 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1738 }; 1739 1740 1741 //memorytype DMI Type 17 offset 12h - Memory Type 1742 enum atom_dmi_t17_mem_type_def{ 1743 OtherMemType = 0x01, ///< Assign 01 to Other 1744 UnknownMemType, ///< Assign 02 to Unknown 1745 DramMemType, ///< Assign 03 to DRAM 1746 EdramMemType, ///< Assign 04 to EDRAM 1747 VramMemType, ///< Assign 05 to VRAM 1748 SramMemType, ///< Assign 06 to SRAM 1749 RamMemType, ///< Assign 07 to RAM 1750 RomMemType, ///< Assign 08 to ROM 1751 FlashMemType, ///< Assign 09 to Flash 1752 EepromMemType, ///< Assign 10 to EEPROM 1753 FepromMemType, ///< Assign 11 to FEPROM 1754 EpromMemType, ///< Assign 12 to EPROM 1755 CdramMemType, ///< Assign 13 to CDRAM 1756 ThreeDramMemType, ///< Assign 14 to 3DRAM 1757 SdramMemType, ///< Assign 15 to SDRAM 1758 SgramMemType, ///< Assign 16 to SGRAM 1759 RdramMemType, ///< Assign 17 to RDRAM 1760 DdrMemType, ///< Assign 18 to DDR 1761 Ddr2MemType, ///< Assign 19 to DDR2 1762 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1763 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1764 Fbd2MemType, ///< Assign 25 to FBD2 1765 Ddr4MemType, ///< Assign 26 to DDR4 1766 LpDdrMemType, ///< Assign 27 to LPDDR 1767 LpDdr2MemType, ///< Assign 28 to LPDDR2 1768 LpDdr3MemType, ///< Assign 29 to LPDDR3 1769 LpDdr4MemType, ///< Assign 30 to LPDDR4 1770 GDdr6MemType, ///< Assign 31 to GDDR6 1771 HbmMemType, ///< Assign 32 to HBM 1772 Hbm2MemType, ///< Assign 33 to HBM2 1773 Ddr5MemType, ///< Assign 34 to DDR5 1774 LpDdr5MemType, ///< Assign 35 to LPDDR5 1775 LpDdr5xMemType, ///< Assign 36 to LPDDR5x 1776 }; 1777 1778 1779 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1780 struct atom_fusion_system_info_v4 1781 { 1782 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1783 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1784 }; 1785 1786 1787 /* 1788 *************************************************************************** 1789 Data Table gfx_info structure 1790 *************************************************************************** 1791 */ 1792 1793 struct atom_gfx_info_v2_2 1794 { 1795 struct atom_common_table_header table_header; 1796 uint8_t gfxip_min_ver; 1797 uint8_t gfxip_max_ver; 1798 uint8_t max_shader_engines; 1799 uint8_t max_tile_pipes; 1800 uint8_t max_cu_per_sh; 1801 uint8_t max_sh_per_se; 1802 uint8_t max_backends_per_se; 1803 uint8_t max_texture_channel_caches; 1804 uint32_t regaddr_cp_dma_src_addr; 1805 uint32_t regaddr_cp_dma_src_addr_hi; 1806 uint32_t regaddr_cp_dma_dst_addr; 1807 uint32_t regaddr_cp_dma_dst_addr_hi; 1808 uint32_t regaddr_cp_dma_command; 1809 uint32_t regaddr_cp_status; 1810 uint32_t regaddr_rlc_gpu_clock_32; 1811 uint32_t rlc_gpu_timer_refclk; 1812 }; 1813 1814 struct atom_gfx_info_v2_3 { 1815 struct atom_common_table_header table_header; 1816 uint8_t gfxip_min_ver; 1817 uint8_t gfxip_max_ver; 1818 uint8_t max_shader_engines; 1819 uint8_t max_tile_pipes; 1820 uint8_t max_cu_per_sh; 1821 uint8_t max_sh_per_se; 1822 uint8_t max_backends_per_se; 1823 uint8_t max_texture_channel_caches; 1824 uint32_t regaddr_cp_dma_src_addr; 1825 uint32_t regaddr_cp_dma_src_addr_hi; 1826 uint32_t regaddr_cp_dma_dst_addr; 1827 uint32_t regaddr_cp_dma_dst_addr_hi; 1828 uint32_t regaddr_cp_dma_command; 1829 uint32_t regaddr_cp_status; 1830 uint32_t regaddr_rlc_gpu_clock_32; 1831 uint32_t rlc_gpu_timer_refclk; 1832 uint8_t active_cu_per_sh; 1833 uint8_t active_rb_per_se; 1834 uint16_t gcgoldenoffset; 1835 uint32_t rm21_sram_vmin_value; 1836 }; 1837 1838 struct atom_gfx_info_v2_4 1839 { 1840 struct atom_common_table_header table_header; 1841 uint8_t gfxip_min_ver; 1842 uint8_t gfxip_max_ver; 1843 uint8_t max_shader_engines; 1844 uint8_t reserved; 1845 uint8_t max_cu_per_sh; 1846 uint8_t max_sh_per_se; 1847 uint8_t max_backends_per_se; 1848 uint8_t max_texture_channel_caches; 1849 uint32_t regaddr_cp_dma_src_addr; 1850 uint32_t regaddr_cp_dma_src_addr_hi; 1851 uint32_t regaddr_cp_dma_dst_addr; 1852 uint32_t regaddr_cp_dma_dst_addr_hi; 1853 uint32_t regaddr_cp_dma_command; 1854 uint32_t regaddr_cp_status; 1855 uint32_t regaddr_rlc_gpu_clock_32; 1856 uint32_t rlc_gpu_timer_refclk; 1857 uint8_t active_cu_per_sh; 1858 uint8_t active_rb_per_se; 1859 uint16_t gcgoldenoffset; 1860 uint16_t gc_num_gprs; 1861 uint16_t gc_gsprim_buff_depth; 1862 uint16_t gc_parameter_cache_depth; 1863 uint16_t gc_wave_size; 1864 uint16_t gc_max_waves_per_simd; 1865 uint16_t gc_lds_size; 1866 uint8_t gc_num_max_gs_thds; 1867 uint8_t gc_gs_table_depth; 1868 uint8_t gc_double_offchip_lds_buffer; 1869 uint8_t gc_max_scratch_slots_per_cu; 1870 uint32_t sram_rm_fuses_val; 1871 uint32_t sram_custom_rm_fuses_val; 1872 }; 1873 1874 struct atom_gfx_info_v2_7 { 1875 struct atom_common_table_header table_header; 1876 uint8_t gfxip_min_ver; 1877 uint8_t gfxip_max_ver; 1878 uint8_t max_shader_engines; 1879 uint8_t reserved; 1880 uint8_t max_cu_per_sh; 1881 uint8_t max_sh_per_se; 1882 uint8_t max_backends_per_se; 1883 uint8_t max_texture_channel_caches; 1884 uint32_t regaddr_cp_dma_src_addr; 1885 uint32_t regaddr_cp_dma_src_addr_hi; 1886 uint32_t regaddr_cp_dma_dst_addr; 1887 uint32_t regaddr_cp_dma_dst_addr_hi; 1888 uint32_t regaddr_cp_dma_command; 1889 uint32_t regaddr_cp_status; 1890 uint32_t regaddr_rlc_gpu_clock_32; 1891 uint32_t rlc_gpu_timer_refclk; 1892 uint8_t active_cu_per_sh; 1893 uint8_t active_rb_per_se; 1894 uint16_t gcgoldenoffset; 1895 uint16_t gc_num_gprs; 1896 uint16_t gc_gsprim_buff_depth; 1897 uint16_t gc_parameter_cache_depth; 1898 uint16_t gc_wave_size; 1899 uint16_t gc_max_waves_per_simd; 1900 uint16_t gc_lds_size; 1901 uint8_t gc_num_max_gs_thds; 1902 uint8_t gc_gs_table_depth; 1903 uint8_t gc_double_offchip_lds_buffer; 1904 uint8_t gc_max_scratch_slots_per_cu; 1905 uint32_t sram_rm_fuses_val; 1906 uint32_t sram_custom_rm_fuses_val; 1907 uint8_t cut_cu; 1908 uint8_t active_cu_total; 1909 uint8_t cu_reserved[2]; 1910 uint32_t gc_config; 1911 uint8_t inactive_cu_per_se[8]; 1912 uint32_t reserved2[6]; 1913 }; 1914 1915 struct atom_gfx_info_v3_0 { 1916 struct atom_common_table_header table_header; 1917 uint8_t gfxip_min_ver; 1918 uint8_t gfxip_max_ver; 1919 uint8_t max_shader_engines; 1920 uint8_t max_tile_pipes; 1921 uint8_t max_cu_per_sh; 1922 uint8_t max_sh_per_se; 1923 uint8_t max_backends_per_se; 1924 uint8_t max_texture_channel_caches; 1925 uint32_t regaddr_lsdma_queue0_rb_rptr; 1926 uint32_t regaddr_lsdma_queue0_rb_rptr_hi; 1927 uint32_t regaddr_lsdma_queue0_rb_wptr; 1928 uint32_t regaddr_lsdma_queue0_rb_wptr_hi; 1929 uint32_t regaddr_lsdma_command; 1930 uint32_t regaddr_lsdma_status; 1931 uint32_t regaddr_golden_tsc_count_lower; 1932 uint32_t golden_tsc_count_lower_refclk; 1933 uint8_t active_wgp_per_se; 1934 uint8_t active_rb_per_se; 1935 uint8_t active_se; 1936 uint8_t reserved1; 1937 uint32_t sram_rm_fuses_val; 1938 uint32_t sram_custom_rm_fuses_val; 1939 uint32_t inactive_sa_mask; 1940 uint32_t gc_config; 1941 uint8_t inactive_wgp[16]; 1942 uint8_t inactive_rb[16]; 1943 uint32_t gdfll_as_wait_ctrl_val; 1944 uint32_t gdfll_as_step_ctrl_val; 1945 uint32_t reserved[8]; 1946 }; 1947 1948 /* 1949 *************************************************************************** 1950 Data Table smu_info structure 1951 *************************************************************************** 1952 */ 1953 struct atom_smu_info_v3_1 1954 { 1955 struct atom_common_table_header table_header; 1956 uint8_t smuip_min_ver; 1957 uint8_t smuip_max_ver; 1958 uint8_t smu_rsd1; 1959 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1960 uint16_t sclk_ss_percentage; 1961 uint16_t sclk_ss_rate_10hz; 1962 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1963 uint16_t gpuclk_ss_rate_10hz; 1964 uint32_t core_refclk_10khz; 1965 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1966 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1967 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1968 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1969 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1970 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1971 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1972 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1973 }; 1974 1975 struct atom_smu_info_v3_2 { 1976 struct atom_common_table_header table_header; 1977 uint8_t smuip_min_ver; 1978 uint8_t smuip_max_ver; 1979 uint8_t smu_rsd1; 1980 uint8_t gpuclk_ss_mode; 1981 uint16_t sclk_ss_percentage; 1982 uint16_t sclk_ss_rate_10hz; 1983 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1984 uint16_t gpuclk_ss_rate_10hz; 1985 uint32_t core_refclk_10khz; 1986 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1987 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1988 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1989 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1990 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1991 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1992 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1993 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1994 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1995 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1996 uint16_t smugoldenoffset; 1997 uint32_t gpupll_vco_freq_10khz; 1998 uint32_t bootup_smnclk_10khz; 1999 uint32_t bootup_socclk_10khz; 2000 uint32_t bootup_mp0clk_10khz; 2001 uint32_t bootup_mp1clk_10khz; 2002 uint32_t bootup_lclk_10khz; 2003 uint32_t bootup_dcefclk_10khz; 2004 uint32_t ctf_threshold_override_value; 2005 uint32_t reserved[5]; 2006 }; 2007 2008 struct atom_smu_info_v3_3 { 2009 struct atom_common_table_header table_header; 2010 uint8_t smuip_min_ver; 2011 uint8_t smuip_max_ver; 2012 uint8_t waflclk_ss_mode; 2013 uint8_t gpuclk_ss_mode; 2014 uint16_t sclk_ss_percentage; 2015 uint16_t sclk_ss_rate_10hz; 2016 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 2017 uint16_t gpuclk_ss_rate_10hz; 2018 uint32_t core_refclk_10khz; 2019 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 2020 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 2021 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 2022 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 2023 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 2024 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 2025 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 2026 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 2027 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 2028 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 2029 uint16_t smugoldenoffset; 2030 uint32_t gpupll_vco_freq_10khz; 2031 uint32_t bootup_smnclk_10khz; 2032 uint32_t bootup_socclk_10khz; 2033 uint32_t bootup_mp0clk_10khz; 2034 uint32_t bootup_mp1clk_10khz; 2035 uint32_t bootup_lclk_10khz; 2036 uint32_t bootup_dcefclk_10khz; 2037 uint32_t ctf_threshold_override_value; 2038 uint32_t syspll3_0_vco_freq_10khz; 2039 uint32_t syspll3_1_vco_freq_10khz; 2040 uint32_t bootup_fclk_10khz; 2041 uint32_t bootup_waflclk_10khz; 2042 uint32_t smu_info_caps; 2043 uint16_t waflclk_ss_percentage; // in unit of 0.001% 2044 uint16_t smuinitoffset; 2045 uint32_t reserved; 2046 }; 2047 2048 struct atom_smu_info_v3_5 2049 { 2050 struct atom_common_table_header table_header; 2051 uint8_t smuip_min_ver; 2052 uint8_t smuip_max_ver; 2053 uint8_t waflclk_ss_mode; 2054 uint8_t gpuclk_ss_mode; 2055 uint16_t sclk_ss_percentage; 2056 uint16_t sclk_ss_rate_10hz; 2057 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 2058 uint16_t gpuclk_ss_rate_10hz; 2059 uint32_t core_refclk_10khz; 2060 uint32_t syspll0_1_vco_freq_10khz; 2061 uint32_t syspll0_2_vco_freq_10khz; 2062 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 2063 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 2064 uint16_t smugoldenoffset; 2065 uint32_t syspll0_0_vco_freq_10khz; 2066 uint32_t bootup_smnclk_10khz; 2067 uint32_t bootup_socclk_10khz; 2068 uint32_t bootup_mp0clk_10khz; 2069 uint32_t bootup_mp1clk_10khz; 2070 uint32_t bootup_lclk_10khz; 2071 uint32_t bootup_dcefclk_10khz; 2072 uint32_t ctf_threshold_override_value; 2073 uint32_t syspll3_0_vco_freq_10khz; 2074 uint32_t syspll3_1_vco_freq_10khz; 2075 uint32_t bootup_fclk_10khz; 2076 uint32_t bootup_waflclk_10khz; 2077 uint32_t smu_info_caps; 2078 uint16_t waflclk_ss_percentage; // in unit of 0.001% 2079 uint16_t smuinitoffset; 2080 uint32_t bootup_dprefclk_10khz; 2081 uint32_t bootup_usbclk_10khz; 2082 uint32_t smb_slave_address; 2083 uint32_t cg_fdo_ctrl0_val; 2084 uint32_t cg_fdo_ctrl1_val; 2085 uint32_t cg_fdo_ctrl2_val; 2086 uint32_t gdfll_as_wait_ctrl_val; 2087 uint32_t gdfll_as_step_ctrl_val; 2088 uint32_t bootup_dtbclk_10khz; 2089 uint32_t fclk_syspll_refclk_10khz; 2090 uint32_t smusvi_svc0_val; 2091 uint32_t smusvi_svc1_val; 2092 uint32_t smusvi_svd0_val; 2093 uint32_t smusvi_svd1_val; 2094 uint32_t smusvi_svt0_val; 2095 uint32_t smusvi_svt1_val; 2096 uint32_t cg_tach_ctrl_val; 2097 uint32_t cg_pump_ctrl1_val; 2098 uint32_t cg_pump_tach_ctrl_val; 2099 uint32_t thm_ctf_delay_val; 2100 uint32_t thm_thermal_int_ctrl_val; 2101 uint32_t thm_tmon_config_val; 2102 uint32_t reserved[16]; 2103 }; 2104 2105 struct atom_smu_info_v3_6 2106 { 2107 struct atom_common_table_header table_header; 2108 uint8_t smuip_min_ver; 2109 uint8_t smuip_max_ver; 2110 uint8_t waflclk_ss_mode; 2111 uint8_t gpuclk_ss_mode; 2112 uint16_t sclk_ss_percentage; 2113 uint16_t sclk_ss_rate_10hz; 2114 uint16_t gpuclk_ss_percentage; 2115 uint16_t gpuclk_ss_rate_10hz; 2116 uint32_t core_refclk_10khz; 2117 uint32_t syspll0_1_vco_freq_10khz; 2118 uint32_t syspll0_2_vco_freq_10khz; 2119 uint8_t pcc_gpio_bit; 2120 uint8_t pcc_gpio_polarity; 2121 uint16_t smugoldenoffset; 2122 uint32_t syspll0_0_vco_freq_10khz; 2123 uint32_t bootup_smnclk_10khz; 2124 uint32_t bootup_socclk_10khz; 2125 uint32_t bootup_mp0clk_10khz; 2126 uint32_t bootup_mp1clk_10khz; 2127 uint32_t bootup_lclk_10khz; 2128 uint32_t bootup_dxioclk_10khz; 2129 uint32_t ctf_threshold_override_value; 2130 uint32_t syspll3_0_vco_freq_10khz; 2131 uint32_t syspll3_1_vco_freq_10khz; 2132 uint32_t bootup_fclk_10khz; 2133 uint32_t bootup_waflclk_10khz; 2134 uint32_t smu_info_caps; 2135 uint16_t waflclk_ss_percentage; 2136 uint16_t smuinitoffset; 2137 uint32_t bootup_gfxavsclk_10khz; 2138 uint32_t bootup_mpioclk_10khz; 2139 uint32_t smb_slave_address; 2140 uint32_t cg_fdo_ctrl0_val; 2141 uint32_t cg_fdo_ctrl1_val; 2142 uint32_t cg_fdo_ctrl2_val; 2143 uint32_t gdfll_as_wait_ctrl_val; 2144 uint32_t gdfll_as_step_ctrl_val; 2145 uint32_t reserved_clk; 2146 uint32_t fclk_syspll_refclk_10khz; 2147 uint32_t smusvi_svc0_val; 2148 uint32_t smusvi_svc1_val; 2149 uint32_t smusvi_svd0_val; 2150 uint32_t smusvi_svd1_val; 2151 uint32_t smusvi_svt0_val; 2152 uint32_t smusvi_svt1_val; 2153 uint32_t cg_tach_ctrl_val; 2154 uint32_t cg_pump_ctrl1_val; 2155 uint32_t cg_pump_tach_ctrl_val; 2156 uint32_t thm_ctf_delay_val; 2157 uint32_t thm_thermal_int_ctrl_val; 2158 uint32_t thm_tmon_config_val; 2159 uint32_t bootup_vclk_10khz; 2160 uint32_t bootup_dclk_10khz; 2161 uint32_t smu_gpiopad_pu_en_val; 2162 uint32_t smu_gpiopad_pd_en_val; 2163 uint32_t reserved[12]; 2164 }; 2165 2166 struct atom_smu_info_v4_0 { 2167 struct atom_common_table_header table_header; 2168 uint32_t bootup_gfxclk_bypass_10khz; 2169 uint32_t bootup_usrclk_10khz; 2170 uint32_t bootup_csrclk_10khz; 2171 uint32_t core_refclk_10khz; 2172 uint32_t syspll1_vco_freq_10khz; 2173 uint32_t syspll2_vco_freq_10khz; 2174 uint8_t pcc_gpio_bit; 2175 uint8_t pcc_gpio_polarity; 2176 uint16_t bootup_vddusr_mv; 2177 uint32_t syspll0_vco_freq_10khz; 2178 uint32_t bootup_smnclk_10khz; 2179 uint32_t bootup_socclk_10khz; 2180 uint32_t bootup_mp0clk_10khz; 2181 uint32_t bootup_mp1clk_10khz; 2182 uint32_t bootup_lclk_10khz; 2183 uint32_t bootup_dcefclk_10khz; 2184 uint32_t ctf_threshold_override_value; 2185 uint32_t syspll3_vco_freq_10khz; 2186 uint32_t mm_syspll_vco_freq_10khz; 2187 uint32_t bootup_fclk_10khz; 2188 uint32_t bootup_waflclk_10khz; 2189 uint32_t smu_info_caps; 2190 uint16_t waflclk_ss_percentage; 2191 uint16_t smuinitoffset; 2192 uint32_t bootup_dprefclk_10khz; 2193 uint32_t bootup_usbclk_10khz; 2194 uint32_t smb_slave_address; 2195 uint32_t cg_fdo_ctrl0_val; 2196 uint32_t cg_fdo_ctrl1_val; 2197 uint32_t cg_fdo_ctrl2_val; 2198 uint32_t gdfll_as_wait_ctrl_val; 2199 uint32_t gdfll_as_step_ctrl_val; 2200 uint32_t bootup_dtbclk_10khz; 2201 uint32_t fclk_syspll_refclk_10khz; 2202 uint32_t smusvi_svc0_val; 2203 uint32_t smusvi_svc1_val; 2204 uint32_t smusvi_svd0_val; 2205 uint32_t smusvi_svd1_val; 2206 uint32_t smusvi_svt0_val; 2207 uint32_t smusvi_svt1_val; 2208 uint32_t cg_tach_ctrl_val; 2209 uint32_t cg_pump_ctrl1_val; 2210 uint32_t cg_pump_tach_ctrl_val; 2211 uint32_t thm_ctf_delay_val; 2212 uint32_t thm_thermal_int_ctrl_val; 2213 uint32_t thm_tmon_config_val; 2214 uint32_t smbus_timing_cntrl0_val; 2215 uint32_t smbus_timing_cntrl1_val; 2216 uint32_t smbus_timing_cntrl2_val; 2217 uint32_t pwr_disp_timer_global_control_val; 2218 uint32_t bootup_mpioclk_10khz; 2219 uint32_t bootup_dclk0_10khz; 2220 uint32_t bootup_vclk0_10khz; 2221 uint32_t bootup_dclk1_10khz; 2222 uint32_t bootup_vclk1_10khz; 2223 uint32_t bootup_baco400clk_10khz; 2224 uint32_t bootup_baco1200clk_bypass_10khz; 2225 uint32_t bootup_baco700clk_bypass_10khz; 2226 uint32_t reserved[16]; 2227 }; 2228 2229 /* 2230 *************************************************************************** 2231 Data Table smc_dpm_info structure 2232 *************************************************************************** 2233 */ 2234 struct atom_smc_dpm_info_v4_1 2235 { 2236 struct atom_common_table_header table_header; 2237 uint8_t liquid1_i2c_address; 2238 uint8_t liquid2_i2c_address; 2239 uint8_t vr_i2c_address; 2240 uint8_t plx_i2c_address; 2241 2242 uint8_t liquid_i2c_linescl; 2243 uint8_t liquid_i2c_linesda; 2244 uint8_t vr_i2c_linescl; 2245 uint8_t vr_i2c_linesda; 2246 2247 uint8_t plx_i2c_linescl; 2248 uint8_t plx_i2c_linesda; 2249 uint8_t vrsensorpresent; 2250 uint8_t liquidsensorpresent; 2251 2252 uint16_t maxvoltagestepgfx; 2253 uint16_t maxvoltagestepsoc; 2254 2255 uint8_t vddgfxvrmapping; 2256 uint8_t vddsocvrmapping; 2257 uint8_t vddmem0vrmapping; 2258 uint8_t vddmem1vrmapping; 2259 2260 uint8_t gfxulvphasesheddingmask; 2261 uint8_t soculvphasesheddingmask; 2262 uint8_t padding8_v[2]; 2263 2264 uint16_t gfxmaxcurrent; 2265 uint8_t gfxoffset; 2266 uint8_t padding_telemetrygfx; 2267 2268 uint16_t socmaxcurrent; 2269 uint8_t socoffset; 2270 uint8_t padding_telemetrysoc; 2271 2272 uint16_t mem0maxcurrent; 2273 uint8_t mem0offset; 2274 uint8_t padding_telemetrymem0; 2275 2276 uint16_t mem1maxcurrent; 2277 uint8_t mem1offset; 2278 uint8_t padding_telemetrymem1; 2279 2280 uint8_t acdcgpio; 2281 uint8_t acdcpolarity; 2282 uint8_t vr0hotgpio; 2283 uint8_t vr0hotpolarity; 2284 2285 uint8_t vr1hotgpio; 2286 uint8_t vr1hotpolarity; 2287 uint8_t padding1; 2288 uint8_t padding2; 2289 2290 uint8_t ledpin0; 2291 uint8_t ledpin1; 2292 uint8_t ledpin2; 2293 uint8_t padding8_4; 2294 2295 uint8_t pllgfxclkspreadenabled; 2296 uint8_t pllgfxclkspreadpercent; 2297 uint16_t pllgfxclkspreadfreq; 2298 2299 uint8_t uclkspreadenabled; 2300 uint8_t uclkspreadpercent; 2301 uint16_t uclkspreadfreq; 2302 2303 uint8_t socclkspreadenabled; 2304 uint8_t socclkspreadpercent; 2305 uint16_t socclkspreadfreq; 2306 2307 uint8_t acggfxclkspreadenabled; 2308 uint8_t acggfxclkspreadpercent; 2309 uint16_t acggfxclkspreadfreq; 2310 2311 uint8_t Vr2_I2C_address; 2312 uint8_t padding_vr2[3]; 2313 2314 uint32_t boardreserved[9]; 2315 }; 2316 2317 /* 2318 *************************************************************************** 2319 Data Table smc_dpm_info structure 2320 *************************************************************************** 2321 */ 2322 struct atom_smc_dpm_info_v4_3 2323 { 2324 struct atom_common_table_header table_header; 2325 uint8_t liquid1_i2c_address; 2326 uint8_t liquid2_i2c_address; 2327 uint8_t vr_i2c_address; 2328 uint8_t plx_i2c_address; 2329 2330 uint8_t liquid_i2c_linescl; 2331 uint8_t liquid_i2c_linesda; 2332 uint8_t vr_i2c_linescl; 2333 uint8_t vr_i2c_linesda; 2334 2335 uint8_t plx_i2c_linescl; 2336 uint8_t plx_i2c_linesda; 2337 uint8_t vrsensorpresent; 2338 uint8_t liquidsensorpresent; 2339 2340 uint16_t maxvoltagestepgfx; 2341 uint16_t maxvoltagestepsoc; 2342 2343 uint8_t vddgfxvrmapping; 2344 uint8_t vddsocvrmapping; 2345 uint8_t vddmem0vrmapping; 2346 uint8_t vddmem1vrmapping; 2347 2348 uint8_t gfxulvphasesheddingmask; 2349 uint8_t soculvphasesheddingmask; 2350 uint8_t externalsensorpresent; 2351 uint8_t padding8_v; 2352 2353 uint16_t gfxmaxcurrent; 2354 uint8_t gfxoffset; 2355 uint8_t padding_telemetrygfx; 2356 2357 uint16_t socmaxcurrent; 2358 uint8_t socoffset; 2359 uint8_t padding_telemetrysoc; 2360 2361 uint16_t mem0maxcurrent; 2362 uint8_t mem0offset; 2363 uint8_t padding_telemetrymem0; 2364 2365 uint16_t mem1maxcurrent; 2366 uint8_t mem1offset; 2367 uint8_t padding_telemetrymem1; 2368 2369 uint8_t acdcgpio; 2370 uint8_t acdcpolarity; 2371 uint8_t vr0hotgpio; 2372 uint8_t vr0hotpolarity; 2373 2374 uint8_t vr1hotgpio; 2375 uint8_t vr1hotpolarity; 2376 uint8_t padding1; 2377 uint8_t padding2; 2378 2379 uint8_t ledpin0; 2380 uint8_t ledpin1; 2381 uint8_t ledpin2; 2382 uint8_t padding8_4; 2383 2384 uint8_t pllgfxclkspreadenabled; 2385 uint8_t pllgfxclkspreadpercent; 2386 uint16_t pllgfxclkspreadfreq; 2387 2388 uint8_t uclkspreadenabled; 2389 uint8_t uclkspreadpercent; 2390 uint16_t uclkspreadfreq; 2391 2392 uint8_t fclkspreadenabled; 2393 uint8_t fclkspreadpercent; 2394 uint16_t fclkspreadfreq; 2395 2396 uint8_t fllgfxclkspreadenabled; 2397 uint8_t fllgfxclkspreadpercent; 2398 uint16_t fllgfxclkspreadfreq; 2399 2400 uint32_t boardreserved[10]; 2401 }; 2402 2403 struct smudpm_i2ccontrollerconfig_t { 2404 uint32_t enabled; 2405 uint32_t slaveaddress; 2406 uint32_t controllerport; 2407 uint32_t controllername; 2408 uint32_t thermalthrottler; 2409 uint32_t i2cprotocol; 2410 uint32_t i2cspeed; 2411 }; 2412 2413 struct atom_smc_dpm_info_v4_4 2414 { 2415 struct atom_common_table_header table_header; 2416 uint32_t i2c_padding[3]; 2417 2418 uint16_t maxvoltagestepgfx; 2419 uint16_t maxvoltagestepsoc; 2420 2421 uint8_t vddgfxvrmapping; 2422 uint8_t vddsocvrmapping; 2423 uint8_t vddmem0vrmapping; 2424 uint8_t vddmem1vrmapping; 2425 2426 uint8_t gfxulvphasesheddingmask; 2427 uint8_t soculvphasesheddingmask; 2428 uint8_t externalsensorpresent; 2429 uint8_t padding8_v; 2430 2431 uint16_t gfxmaxcurrent; 2432 uint8_t gfxoffset; 2433 uint8_t padding_telemetrygfx; 2434 2435 uint16_t socmaxcurrent; 2436 uint8_t socoffset; 2437 uint8_t padding_telemetrysoc; 2438 2439 uint16_t mem0maxcurrent; 2440 uint8_t mem0offset; 2441 uint8_t padding_telemetrymem0; 2442 2443 uint16_t mem1maxcurrent; 2444 uint8_t mem1offset; 2445 uint8_t padding_telemetrymem1; 2446 2447 2448 uint8_t acdcgpio; 2449 uint8_t acdcpolarity; 2450 uint8_t vr0hotgpio; 2451 uint8_t vr0hotpolarity; 2452 2453 uint8_t vr1hotgpio; 2454 uint8_t vr1hotpolarity; 2455 uint8_t padding1; 2456 uint8_t padding2; 2457 2458 2459 uint8_t ledpin0; 2460 uint8_t ledpin1; 2461 uint8_t ledpin2; 2462 uint8_t padding8_4; 2463 2464 2465 uint8_t pllgfxclkspreadenabled; 2466 uint8_t pllgfxclkspreadpercent; 2467 uint16_t pllgfxclkspreadfreq; 2468 2469 2470 uint8_t uclkspreadenabled; 2471 uint8_t uclkspreadpercent; 2472 uint16_t uclkspreadfreq; 2473 2474 2475 uint8_t fclkspreadenabled; 2476 uint8_t fclkspreadpercent; 2477 uint16_t fclkspreadfreq; 2478 2479 2480 uint8_t fllgfxclkspreadenabled; 2481 uint8_t fllgfxclkspreadpercent; 2482 uint16_t fllgfxclkspreadfreq; 2483 2484 2485 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 2486 2487 2488 uint32_t boardreserved[10]; 2489 }; 2490 2491 enum smudpm_v4_5_i2ccontrollername_e{ 2492 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 2493 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 2494 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 2495 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 2496 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 2497 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 2498 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 2499 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 2500 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 2501 }; 2502 2503 enum smudpm_v4_5_i2ccontrollerthrottler_e{ 2504 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 2505 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 2506 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 2507 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 2508 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 2509 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 2510 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 2511 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 2512 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 2513 }; 2514 2515 enum smudpm_v4_5_i2ccontrollerprotocol_e{ 2516 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 2517 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 2518 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 2519 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 2520 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 2521 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 2522 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 2523 }; 2524 2525 struct smudpm_i2c_controller_config_v2 2526 { 2527 uint8_t Enabled; 2528 uint8_t Speed; 2529 uint8_t Padding[2]; 2530 uint32_t SlaveAddress; 2531 uint8_t ControllerPort; 2532 uint8_t ControllerName; 2533 uint8_t ThermalThrotter; 2534 uint8_t I2cProtocol; 2535 }; 2536 2537 struct atom_smc_dpm_info_v4_5 2538 { 2539 struct atom_common_table_header table_header; 2540 // SECTION: BOARD PARAMETERS 2541 // I2C Control 2542 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2543 2544 // SVI2 Board Parameters 2545 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2546 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2547 2548 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2549 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2550 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2551 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2552 2553 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2554 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2555 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2556 uint8_t Padding8_V; 2557 2558 // Telemetry Settings 2559 uint16_t GfxMaxCurrent; // in Amps 2560 uint8_t GfxOffset; // in Amps 2561 uint8_t Padding_TelemetryGfx; 2562 uint16_t SocMaxCurrent; // in Amps 2563 uint8_t SocOffset; // in Amps 2564 uint8_t Padding_TelemetrySoc; 2565 2566 uint16_t Mem0MaxCurrent; // in Amps 2567 uint8_t Mem0Offset; // in Amps 2568 uint8_t Padding_TelemetryMem0; 2569 2570 uint16_t Mem1MaxCurrent; // in Amps 2571 uint8_t Mem1Offset; // in Amps 2572 uint8_t Padding_TelemetryMem1; 2573 2574 // GPIO Settings 2575 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2576 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2577 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2578 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2579 2580 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2581 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2582 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2583 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2584 2585 // LED Display Settings 2586 uint8_t LedPin0; // GPIO number for LedPin[0] 2587 uint8_t LedPin1; // GPIO number for LedPin[1] 2588 uint8_t LedPin2; // GPIO number for LedPin[2] 2589 uint8_t padding8_4; 2590 2591 // GFXCLK PLL Spread Spectrum 2592 uint8_t PllGfxclkSpreadEnabled; // on or off 2593 uint8_t PllGfxclkSpreadPercent; // Q4.4 2594 uint16_t PllGfxclkSpreadFreq; // kHz 2595 2596 // GFXCLK DFLL Spread Spectrum 2597 uint8_t DfllGfxclkSpreadEnabled; // on or off 2598 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2599 uint16_t DfllGfxclkSpreadFreq; // kHz 2600 2601 // UCLK Spread Spectrum 2602 uint8_t UclkSpreadEnabled; // on or off 2603 uint8_t UclkSpreadPercent; // Q4.4 2604 uint16_t UclkSpreadFreq; // kHz 2605 2606 // SOCCLK Spread Spectrum 2607 uint8_t SoclkSpreadEnabled; // on or off 2608 uint8_t SocclkSpreadPercent; // Q4.4 2609 uint16_t SocclkSpreadFreq; // kHz 2610 2611 // Total board power 2612 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2613 uint16_t BoardPadding; 2614 2615 // Mvdd Svi2 Div Ratio Setting 2616 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2617 2618 uint32_t BoardReserved[9]; 2619 2620 }; 2621 2622 struct atom_smc_dpm_info_v4_6 2623 { 2624 struct atom_common_table_header table_header; 2625 // section: board parameters 2626 uint32_t i2c_padding[3]; // old i2c control are moved to new area 2627 2628 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2629 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2630 2631 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 2632 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 2633 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 2634 uint8_t boardvrmapping; // use vr_mapping* bitfields 2635 2636 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 2637 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 2638 uint8_t padding8_v[2]; 2639 2640 // telemetry settings 2641 uint16_t gfxmaxcurrent; // in amps 2642 uint8_t gfxoffset; // in amps 2643 uint8_t padding_telemetrygfx; 2644 2645 uint16_t socmaxcurrent; // in amps 2646 uint8_t socoffset; // in amps 2647 uint8_t padding_telemetrysoc; 2648 2649 uint16_t memmaxcurrent; // in amps 2650 uint8_t memoffset; // in amps 2651 uint8_t padding_telemetrymem; 2652 2653 uint16_t boardmaxcurrent; // in amps 2654 uint8_t boardoffset; // in amps 2655 uint8_t padding_telemetryboardinput; 2656 2657 // gpio settings 2658 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 2659 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 2660 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 2661 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 2662 2663 // gfxclk pll spread spectrum 2664 uint8_t pllgfxclkspreadenabled; // on or off 2665 uint8_t pllgfxclkspreadpercent; // q4.4 2666 uint16_t pllgfxclkspreadfreq; // khz 2667 2668 // uclk spread spectrum 2669 uint8_t uclkspreadenabled; // on or off 2670 uint8_t uclkspreadpercent; // q4.4 2671 uint16_t uclkspreadfreq; // khz 2672 2673 // fclk spread spectrum 2674 uint8_t fclkspreadenabled; // on or off 2675 uint8_t fclkspreadpercent; // q4.4 2676 uint16_t fclkspreadfreq; // khz 2677 2678 2679 // gfxclk fll spread spectrum 2680 uint8_t fllgfxclkspreadenabled; // on or off 2681 uint8_t fllgfxclkspreadpercent; // q4.4 2682 uint16_t fllgfxclkspreadfreq; // khz 2683 2684 // i2c controller structure 2685 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 2686 2687 // memory section 2688 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 2689 2690 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 2691 uint8_t paddingmem[3]; 2692 2693 // total board power 2694 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 2695 uint16_t boardpadding; 2696 2697 // section: xgmi training 2698 uint8_t xgmilinkspeed[4]; 2699 uint8_t xgmilinkwidth[4]; 2700 2701 uint16_t xgmifclkfreq[4]; 2702 uint16_t xgmisocvoltage[4]; 2703 2704 // reserved 2705 uint32_t boardreserved[10]; 2706 }; 2707 2708 struct atom_smc_dpm_info_v4_7 2709 { 2710 struct atom_common_table_header table_header; 2711 // SECTION: BOARD PARAMETERS 2712 // I2C Control 2713 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2714 2715 // SVI2 Board Parameters 2716 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2717 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2718 2719 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2720 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2721 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2722 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2723 2724 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2725 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2726 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2727 uint8_t Padding8_V; 2728 2729 // Telemetry Settings 2730 uint16_t GfxMaxCurrent; // in Amps 2731 uint8_t GfxOffset; // in Amps 2732 uint8_t Padding_TelemetryGfx; 2733 uint16_t SocMaxCurrent; // in Amps 2734 uint8_t SocOffset; // in Amps 2735 uint8_t Padding_TelemetrySoc; 2736 2737 uint16_t Mem0MaxCurrent; // in Amps 2738 uint8_t Mem0Offset; // in Amps 2739 uint8_t Padding_TelemetryMem0; 2740 2741 uint16_t Mem1MaxCurrent; // in Amps 2742 uint8_t Mem1Offset; // in Amps 2743 uint8_t Padding_TelemetryMem1; 2744 2745 // GPIO Settings 2746 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2747 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2748 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2749 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2750 2751 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2752 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2753 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2754 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2755 2756 // LED Display Settings 2757 uint8_t LedPin0; // GPIO number for LedPin[0] 2758 uint8_t LedPin1; // GPIO number for LedPin[1] 2759 uint8_t LedPin2; // GPIO number for LedPin[2] 2760 uint8_t padding8_4; 2761 2762 // GFXCLK PLL Spread Spectrum 2763 uint8_t PllGfxclkSpreadEnabled; // on or off 2764 uint8_t PllGfxclkSpreadPercent; // Q4.4 2765 uint16_t PllGfxclkSpreadFreq; // kHz 2766 2767 // GFXCLK DFLL Spread Spectrum 2768 uint8_t DfllGfxclkSpreadEnabled; // on or off 2769 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2770 uint16_t DfllGfxclkSpreadFreq; // kHz 2771 2772 // UCLK Spread Spectrum 2773 uint8_t UclkSpreadEnabled; // on or off 2774 uint8_t UclkSpreadPercent; // Q4.4 2775 uint16_t UclkSpreadFreq; // kHz 2776 2777 // SOCCLK Spread Spectrum 2778 uint8_t SoclkSpreadEnabled; // on or off 2779 uint8_t SocclkSpreadPercent; // Q4.4 2780 uint16_t SocclkSpreadFreq; // kHz 2781 2782 // Total board power 2783 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2784 uint16_t BoardPadding; 2785 2786 // Mvdd Svi2 Div Ratio Setting 2787 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2788 2789 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2790 uint8_t GpioI2cScl; // Serial Clock 2791 uint8_t GpioI2cSda; // Serial Data 2792 uint16_t GpioPadding; 2793 2794 // Additional LED Display Settings 2795 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed 2796 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status 2797 uint16_t LedEnableMask; 2798 2799 // Power Limit Scalars 2800 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT] 2801 2802 uint8_t MvddUlvPhaseSheddingMask; 2803 uint8_t VddciUlvPhaseSheddingMask; 2804 uint8_t Padding8_Psi1; 2805 uint8_t Padding8_Psi2; 2806 2807 uint32_t BoardReserved[5]; 2808 }; 2809 2810 struct smudpm_i2c_controller_config_v3 2811 { 2812 uint8_t Enabled; 2813 uint8_t Speed; 2814 uint8_t SlaveAddress; 2815 uint8_t ControllerPort; 2816 uint8_t ControllerName; 2817 uint8_t ThermalThrotter; 2818 uint8_t I2cProtocol; 2819 uint8_t PaddingConfig; 2820 }; 2821 2822 struct atom_smc_dpm_info_v4_9 2823 { 2824 struct atom_common_table_header table_header; 2825 2826 //SECTION: Gaming Clocks 2827 //uint32_t GamingClk[6]; 2828 2829 // SECTION: I2C Control 2830 struct smudpm_i2c_controller_config_v3 I2cControllers[16]; 2831 2832 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 2833 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 2834 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 2835 uint8_t I2cSpare; 2836 2837 // SECTION: SVI2 Board Parameters 2838 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2839 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2840 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2841 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2842 2843 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2844 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2845 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2846 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2847 2848 // SECTION: Telemetry Settings 2849 uint16_t GfxMaxCurrent; // in Amps 2850 uint8_t GfxOffset; // in Amps 2851 uint8_t Padding_TelemetryGfx; 2852 2853 uint16_t SocMaxCurrent; // in Amps 2854 uint8_t SocOffset; // in Amps 2855 uint8_t Padding_TelemetrySoc; 2856 2857 uint16_t Mem0MaxCurrent; // in Amps 2858 uint8_t Mem0Offset; // in Amps 2859 uint8_t Padding_TelemetryMem0; 2860 2861 uint16_t Mem1MaxCurrent; // in Amps 2862 uint8_t Mem1Offset; // in Amps 2863 uint8_t Padding_TelemetryMem1; 2864 2865 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 2866 2867 // SECTION: GPIO Settings 2868 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2869 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2870 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2871 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2872 2873 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2874 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2875 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2876 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2877 2878 // LED Display Settings 2879 uint8_t LedPin0; // GPIO number for LedPin[0] 2880 uint8_t LedPin1; // GPIO number for LedPin[1] 2881 uint8_t LedPin2; // GPIO number for LedPin[2] 2882 uint8_t LedEnableMask; 2883 2884 uint8_t LedPcie; // GPIO number for PCIE results 2885 uint8_t LedError; // GPIO number for Error Cases 2886 uint8_t LedSpare1[2]; 2887 2888 // SECTION: Clock Spread Spectrum 2889 2890 // GFXCLK PLL Spread Spectrum 2891 uint8_t PllGfxclkSpreadEnabled; // on or off 2892 uint8_t PllGfxclkSpreadPercent; // Q4.4 2893 uint16_t PllGfxclkSpreadFreq; // kHz 2894 2895 // GFXCLK DFLL Spread Spectrum 2896 uint8_t DfllGfxclkSpreadEnabled; // on or off 2897 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2898 uint16_t DfllGfxclkSpreadFreq; // kHz 2899 2900 // UCLK Spread Spectrum 2901 uint8_t UclkSpreadEnabled; // on or off 2902 uint8_t UclkSpreadPercent; // Q4.4 2903 uint16_t UclkSpreadFreq; // kHz 2904 2905 // FCLK Spread Spectrum 2906 uint8_t FclkSpreadEnabled; // on or off 2907 uint8_t FclkSpreadPercent; // Q4.4 2908 uint16_t FclkSpreadFreq; // kHz 2909 2910 // Section: Memory Config 2911 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 2912 2913 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 2914 uint8_t PaddingMem1[3]; 2915 2916 // Section: Total Board Power 2917 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2918 uint16_t BoardPowerPadding; 2919 2920 // SECTION: XGMI Training 2921 uint8_t XgmiLinkSpeed [4]; 2922 uint8_t XgmiLinkWidth [4]; 2923 2924 uint16_t XgmiFclkFreq [4]; 2925 uint16_t XgmiSocVoltage [4]; 2926 2927 // SECTION: Board Reserved 2928 2929 uint32_t BoardReserved[16]; 2930 2931 }; 2932 2933 struct atom_smc_dpm_info_v4_10 2934 { 2935 struct atom_common_table_header table_header; 2936 2937 // SECTION: BOARD PARAMETERS 2938 // Telemetry Settings 2939 uint16_t GfxMaxCurrent; // in Amps 2940 uint8_t GfxOffset; // in Amps 2941 uint8_t Padding_TelemetryGfx; 2942 2943 uint16_t SocMaxCurrent; // in Amps 2944 uint8_t SocOffset; // in Amps 2945 uint8_t Padding_TelemetrySoc; 2946 2947 uint16_t MemMaxCurrent; // in Amps 2948 uint8_t MemOffset; // in Amps 2949 uint8_t Padding_TelemetryMem; 2950 2951 uint16_t BoardMaxCurrent; // in Amps 2952 uint8_t BoardOffset; // in Amps 2953 uint8_t Padding_TelemetryBoardInput; 2954 2955 // Platform input telemetry voltage coefficient 2956 uint32_t BoardVoltageCoeffA; // decode by /1000 2957 uint32_t BoardVoltageCoeffB; // decode by /1000 2958 2959 // GPIO Settings 2960 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2961 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2962 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2963 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2964 2965 // UCLK Spread Spectrum 2966 uint8_t UclkSpreadEnabled; // on or off 2967 uint8_t UclkSpreadPercent; // Q4.4 2968 uint16_t UclkSpreadFreq; // kHz 2969 2970 // FCLK Spread Spectrum 2971 uint8_t FclkSpreadEnabled; // on or off 2972 uint8_t FclkSpreadPercent; // Q4.4 2973 uint16_t FclkSpreadFreq; // kHz 2974 2975 // I2C Controller Structure 2976 struct smudpm_i2c_controller_config_v3 I2cControllers[8]; 2977 2978 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2979 uint8_t GpioI2cScl; // Serial Clock 2980 uint8_t GpioI2cSda; // Serial Data 2981 uint16_t spare5; 2982 2983 uint32_t reserved[16]; 2984 }; 2985 2986 /* 2987 *************************************************************************** 2988 Data Table asic_profiling_info structure 2989 *************************************************************************** 2990 */ 2991 struct atom_asic_profiling_info_v4_1 2992 { 2993 struct atom_common_table_header table_header; 2994 uint32_t maxvddc; 2995 uint32_t minvddc; 2996 uint32_t avfs_meannsigma_acontant0; 2997 uint32_t avfs_meannsigma_acontant1; 2998 uint32_t avfs_meannsigma_acontant2; 2999 uint16_t avfs_meannsigma_dc_tol_sigma; 3000 uint16_t avfs_meannsigma_platform_mean; 3001 uint16_t avfs_meannsigma_platform_sigma; 3002 uint32_t gb_vdroop_table_cksoff_a0; 3003 uint32_t gb_vdroop_table_cksoff_a1; 3004 uint32_t gb_vdroop_table_cksoff_a2; 3005 uint32_t gb_vdroop_table_ckson_a0; 3006 uint32_t gb_vdroop_table_ckson_a1; 3007 uint32_t gb_vdroop_table_ckson_a2; 3008 uint32_t avfsgb_fuse_table_cksoff_m1; 3009 uint32_t avfsgb_fuse_table_cksoff_m2; 3010 uint32_t avfsgb_fuse_table_cksoff_b; 3011 uint32_t avfsgb_fuse_table_ckson_m1; 3012 uint32_t avfsgb_fuse_table_ckson_m2; 3013 uint32_t avfsgb_fuse_table_ckson_b; 3014 uint16_t max_voltage_0_25mv; 3015 uint8_t enable_gb_vdroop_table_cksoff; 3016 uint8_t enable_gb_vdroop_table_ckson; 3017 uint8_t enable_gb_fuse_table_cksoff; 3018 uint8_t enable_gb_fuse_table_ckson; 3019 uint16_t psm_age_comfactor; 3020 uint8_t enable_apply_avfs_cksoff_voltage; 3021 uint8_t reserved; 3022 uint32_t dispclk2gfxclk_a; 3023 uint32_t dispclk2gfxclk_b; 3024 uint32_t dispclk2gfxclk_c; 3025 uint32_t pixclk2gfxclk_a; 3026 uint32_t pixclk2gfxclk_b; 3027 uint32_t pixclk2gfxclk_c; 3028 uint32_t dcefclk2gfxclk_a; 3029 uint32_t dcefclk2gfxclk_b; 3030 uint32_t dcefclk2gfxclk_c; 3031 uint32_t phyclk2gfxclk_a; 3032 uint32_t phyclk2gfxclk_b; 3033 uint32_t phyclk2gfxclk_c; 3034 }; 3035 3036 struct atom_asic_profiling_info_v4_2 { 3037 struct atom_common_table_header table_header; 3038 uint32_t maxvddc; 3039 uint32_t minvddc; 3040 uint32_t avfs_meannsigma_acontant0; 3041 uint32_t avfs_meannsigma_acontant1; 3042 uint32_t avfs_meannsigma_acontant2; 3043 uint16_t avfs_meannsigma_dc_tol_sigma; 3044 uint16_t avfs_meannsigma_platform_mean; 3045 uint16_t avfs_meannsigma_platform_sigma; 3046 uint32_t gb_vdroop_table_cksoff_a0; 3047 uint32_t gb_vdroop_table_cksoff_a1; 3048 uint32_t gb_vdroop_table_cksoff_a2; 3049 uint32_t gb_vdroop_table_ckson_a0; 3050 uint32_t gb_vdroop_table_ckson_a1; 3051 uint32_t gb_vdroop_table_ckson_a2; 3052 uint32_t avfsgb_fuse_table_cksoff_m1; 3053 uint32_t avfsgb_fuse_table_cksoff_m2; 3054 uint32_t avfsgb_fuse_table_cksoff_b; 3055 uint32_t avfsgb_fuse_table_ckson_m1; 3056 uint32_t avfsgb_fuse_table_ckson_m2; 3057 uint32_t avfsgb_fuse_table_ckson_b; 3058 uint16_t max_voltage_0_25mv; 3059 uint8_t enable_gb_vdroop_table_cksoff; 3060 uint8_t enable_gb_vdroop_table_ckson; 3061 uint8_t enable_gb_fuse_table_cksoff; 3062 uint8_t enable_gb_fuse_table_ckson; 3063 uint16_t psm_age_comfactor; 3064 uint8_t enable_apply_avfs_cksoff_voltage; 3065 uint8_t reserved; 3066 uint32_t dispclk2gfxclk_a; 3067 uint32_t dispclk2gfxclk_b; 3068 uint32_t dispclk2gfxclk_c; 3069 uint32_t pixclk2gfxclk_a; 3070 uint32_t pixclk2gfxclk_b; 3071 uint32_t pixclk2gfxclk_c; 3072 uint32_t dcefclk2gfxclk_a; 3073 uint32_t dcefclk2gfxclk_b; 3074 uint32_t dcefclk2gfxclk_c; 3075 uint32_t phyclk2gfxclk_a; 3076 uint32_t phyclk2gfxclk_b; 3077 uint32_t phyclk2gfxclk_c; 3078 uint32_t acg_gb_vdroop_table_a0; 3079 uint32_t acg_gb_vdroop_table_a1; 3080 uint32_t acg_gb_vdroop_table_a2; 3081 uint32_t acg_avfsgb_fuse_table_m1; 3082 uint32_t acg_avfsgb_fuse_table_m2; 3083 uint32_t acg_avfsgb_fuse_table_b; 3084 uint8_t enable_acg_gb_vdroop_table; 3085 uint8_t enable_acg_gb_fuse_table; 3086 uint32_t acg_dispclk2gfxclk_a; 3087 uint32_t acg_dispclk2gfxclk_b; 3088 uint32_t acg_dispclk2gfxclk_c; 3089 uint32_t acg_pixclk2gfxclk_a; 3090 uint32_t acg_pixclk2gfxclk_b; 3091 uint32_t acg_pixclk2gfxclk_c; 3092 uint32_t acg_dcefclk2gfxclk_a; 3093 uint32_t acg_dcefclk2gfxclk_b; 3094 uint32_t acg_dcefclk2gfxclk_c; 3095 uint32_t acg_phyclk2gfxclk_a; 3096 uint32_t acg_phyclk2gfxclk_b; 3097 uint32_t acg_phyclk2gfxclk_c; 3098 }; 3099 3100 /* 3101 *************************************************************************** 3102 Data Table multimedia_info structure 3103 *************************************************************************** 3104 */ 3105 struct atom_multimedia_info_v2_1 3106 { 3107 struct atom_common_table_header table_header; 3108 uint8_t uvdip_min_ver; 3109 uint8_t uvdip_max_ver; 3110 uint8_t vceip_min_ver; 3111 uint8_t vceip_max_ver; 3112 uint16_t uvd_enc_max_input_width_pixels; 3113 uint16_t uvd_enc_max_input_height_pixels; 3114 uint16_t vce_enc_max_input_width_pixels; 3115 uint16_t vce_enc_max_input_height_pixels; 3116 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 3117 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 3118 }; 3119 3120 3121 /* 3122 *************************************************************************** 3123 Data Table umc_info structure 3124 *************************************************************************** 3125 */ 3126 struct atom_umc_info_v3_1 3127 { 3128 struct atom_common_table_header table_header; 3129 uint32_t ucode_version; 3130 uint32_t ucode_rom_startaddr; 3131 uint32_t ucode_length; 3132 uint16_t umc_reg_init_offset; 3133 uint16_t customer_ucode_name_offset; 3134 uint16_t mclk_ss_percentage; 3135 uint16_t mclk_ss_rate_10hz; 3136 uint8_t umcip_min_ver; 3137 uint8_t umcip_max_ver; 3138 uint8_t vram_type; //enum of atom_dgpu_vram_type 3139 uint8_t umc_config; 3140 uint32_t mem_refclk_10khz; 3141 }; 3142 3143 // umc_info.umc_config 3144 enum atom_umc_config_def { 3145 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 3146 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 3147 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 3148 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 3149 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 3150 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 3151 }; 3152 3153 struct atom_umc_info_v3_2 3154 { 3155 struct atom_common_table_header table_header; 3156 uint32_t ucode_version; 3157 uint32_t ucode_rom_startaddr; 3158 uint32_t ucode_length; 3159 uint16_t umc_reg_init_offset; 3160 uint16_t customer_ucode_name_offset; 3161 uint16_t mclk_ss_percentage; 3162 uint16_t mclk_ss_rate_10hz; 3163 uint8_t umcip_min_ver; 3164 uint8_t umcip_max_ver; 3165 uint8_t vram_type; //enum of atom_dgpu_vram_type 3166 uint8_t umc_config; 3167 uint32_t mem_refclk_10khz; 3168 uint32_t pstate_uclk_10khz[4]; 3169 uint16_t umcgoldenoffset; 3170 uint16_t densitygoldenoffset; 3171 }; 3172 3173 struct atom_umc_info_v3_3 3174 { 3175 struct atom_common_table_header table_header; 3176 uint32_t ucode_reserved; 3177 uint32_t ucode_rom_startaddr; 3178 uint32_t ucode_length; 3179 uint16_t umc_reg_init_offset; 3180 uint16_t customer_ucode_name_offset; 3181 uint16_t mclk_ss_percentage; 3182 uint16_t mclk_ss_rate_10hz; 3183 uint8_t umcip_min_ver; 3184 uint8_t umcip_max_ver; 3185 uint8_t vram_type; //enum of atom_dgpu_vram_type 3186 uint8_t umc_config; 3187 uint32_t mem_refclk_10khz; 3188 uint32_t pstate_uclk_10khz[4]; 3189 uint16_t umcgoldenoffset; 3190 uint16_t densitygoldenoffset; 3191 uint32_t umc_config1; 3192 uint32_t bist_data_startaddr; 3193 uint32_t reserved[2]; 3194 }; 3195 3196 enum atom_umc_config1_def { 3197 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001, 3198 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002, 3199 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004, 3200 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008, 3201 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010, 3202 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, 3203 }; 3204 3205 struct atom_umc_info_v4_0 { 3206 struct atom_common_table_header table_header; 3207 uint32_t ucode_reserved[5]; 3208 uint8_t umcip_min_ver; 3209 uint8_t umcip_max_ver; 3210 uint8_t vram_type; 3211 uint8_t umc_config; 3212 uint32_t mem_refclk_10khz; 3213 uint32_t clk_reserved[4]; 3214 uint32_t golden_reserved; 3215 uint32_t umc_config1; 3216 uint32_t reserved[2]; 3217 uint8_t channel_num; 3218 uint8_t channel_width; 3219 uint8_t channel_reserve[2]; 3220 uint8_t umc_info_reserved[16]; 3221 }; 3222 3223 /* 3224 *************************************************************************** 3225 Data Table vram_info structure 3226 *************************************************************************** 3227 */ 3228 struct atom_vram_module_v9 { 3229 // Design Specific Values 3230 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3231 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3232 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 3233 uint16_t reserved[3]; 3234 uint16_t mem_voltage; // mem_voltage 3235 uint16_t vram_module_size; // Size of atom_vram_module_v9 3236 uint8_t ext_memory_id; // Current memory module ID 3237 uint8_t memory_type; // enum of atom_dgpu_vram_type 3238 uint8_t channel_num; // Number of mem. channels supported in this module 3239 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3240 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3241 uint8_t tunningset_id; // MC phy registers set per. 3242 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3243 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3244 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 3245 uint8_t vram_rsd2; // reserved 3246 char dram_pnstring[20]; // part number end with '0'. 3247 }; 3248 3249 struct atom_vram_info_header_v2_3 { 3250 struct atom_common_table_header table_header; 3251 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 3252 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 3253 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3254 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3255 uint16_t dram_data_remap_tbloffset; // reserved for now 3256 uint16_t tmrs_seq_offset; // offset of HBM tmrs 3257 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3258 uint16_t vram_rsd2; 3259 uint8_t vram_module_num; // indicate number of VRAM module 3260 uint8_t umcip_min_ver; 3261 uint8_t umcip_max_ver; 3262 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3263 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3264 }; 3265 3266 /* 3267 *************************************************************************** 3268 Data Table vram_info v3.0 structure 3269 *************************************************************************** 3270 */ 3271 struct atom_vram_module_v3_0 { 3272 uint8_t density; 3273 uint8_t tunningset_id; 3274 uint8_t ext_memory_id; 3275 uint8_t dram_vendor_id; 3276 uint16_t dram_info_offset; 3277 uint16_t mem_tuning_offset; 3278 uint16_t tmrs_seq_offset; 3279 uint16_t reserved1; 3280 uint32_t dram_size_per_ch; 3281 uint32_t reserved[3]; 3282 char dram_pnstring[40]; 3283 }; 3284 3285 struct atom_vram_info_header_v3_0 { 3286 struct atom_common_table_header table_header; 3287 uint16_t mem_tuning_table_offset; 3288 uint16_t dram_info_table_offset; 3289 uint16_t tmrs_table_offset; 3290 uint16_t mc_init_table_offset; 3291 uint16_t dram_data_remap_table_offset; 3292 uint16_t umc_emuinittable_offset; 3293 uint16_t reserved_sub_table_offset[2]; 3294 uint8_t vram_module_num; 3295 uint8_t umcip_min_ver; 3296 uint8_t umcip_max_ver; 3297 uint8_t mc_phy_tile_num; 3298 uint8_t memory_type; 3299 uint8_t channel_num; 3300 uint8_t channel_width; 3301 uint8_t reserved1; 3302 uint32_t channel_enable; 3303 uint32_t channel1_enable; 3304 uint32_t feature_enable; 3305 uint32_t feature1_enable; 3306 uint32_t hardcode_mem_size; 3307 uint32_t reserved4[4]; 3308 struct atom_vram_module_v3_0 vram_module[8]; 3309 }; 3310 3311 struct atom_umc_register_addr_info{ 3312 uint32_t umc_register_addr:24; 3313 uint32_t umc_reg_type_ind:1; 3314 uint32_t umc_reg_rsvd:7; 3315 }; 3316 3317 //atom_umc_register_addr_info. 3318 enum atom_umc_register_addr_info_flag{ 3319 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 3320 }; 3321 3322 union atom_umc_register_addr_info_access 3323 { 3324 struct atom_umc_register_addr_info umc_reg_addr; 3325 uint32_t u32umc_reg_addr; 3326 }; 3327 3328 struct atom_umc_reg_setting_id_config{ 3329 uint32_t memclockrange:24; 3330 uint32_t mem_blk_id:8; 3331 }; 3332 3333 union atom_umc_reg_setting_id_config_access 3334 { 3335 struct atom_umc_reg_setting_id_config umc_id_access; 3336 uint32_t u32umc_id_access; 3337 }; 3338 3339 struct atom_umc_reg_setting_data_block{ 3340 union atom_umc_reg_setting_id_config_access block_id; 3341 uint32_t u32umc_reg_data[1]; 3342 }; 3343 3344 struct atom_umc_init_reg_block{ 3345 uint16_t umc_reg_num; 3346 uint16_t reserved; 3347 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 3348 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 3349 }; 3350 3351 struct atom_vram_module_v10 { 3352 // Design Specific Values 3353 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3354 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3355 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 3356 uint16_t reserved[3]; 3357 uint16_t mem_voltage; // mem_voltage 3358 uint16_t vram_module_size; // Size of atom_vram_module_v9 3359 uint8_t ext_memory_id; // Current memory module ID 3360 uint8_t memory_type; // enum of atom_dgpu_vram_type 3361 uint8_t channel_num; // Number of mem. channels supported in this module 3362 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3363 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3364 uint8_t tunningset_id; // MC phy registers set per 3365 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3366 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3367 uint8_t vram_flags; // bit0= bankgroup enable 3368 uint8_t vram_rsd2; // reserved 3369 uint16_t gddr6_mr10; // gddr6 mode register10 value 3370 uint16_t gddr6_mr1; // gddr6 mode register1 value 3371 uint16_t gddr6_mr2; // gddr6 mode register2 value 3372 uint16_t gddr6_mr7; // gddr6 mode register7 value 3373 char dram_pnstring[20]; // part number end with '0' 3374 }; 3375 3376 struct atom_vram_info_header_v2_4 { 3377 struct atom_common_table_header table_header; 3378 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 3379 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 3380 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3381 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3382 uint16_t dram_data_remap_tbloffset; // reserved for now 3383 uint16_t reserved; // offset of reserved 3384 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3385 uint16_t vram_rsd2; 3386 uint8_t vram_module_num; // indicate number of VRAM module 3387 uint8_t umcip_min_ver; 3388 uint8_t umcip_max_ver; 3389 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3390 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3391 }; 3392 3393 struct atom_vram_module_v11 { 3394 // Design Specific Values 3395 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3396 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3397 uint16_t mem_voltage; // mem_voltage 3398 uint16_t vram_module_size; // Size of atom_vram_module_v9 3399 uint8_t ext_memory_id; // Current memory module ID 3400 uint8_t memory_type; // enum of atom_dgpu_vram_type 3401 uint8_t channel_num; // Number of mem. channels supported in this module 3402 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3403 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3404 uint8_t tunningset_id; // MC phy registers set per. 3405 uint16_t reserved[4]; // reserved 3406 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3407 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3408 uint8_t vram_flags; // bit0= bankgroup enable 3409 uint8_t vram_rsd2; // reserved 3410 uint16_t gddr6_mr10; // gddr6 mode register10 value 3411 uint16_t gddr6_mr0; // gddr6 mode register0 value 3412 uint16_t gddr6_mr1; // gddr6 mode register1 value 3413 uint16_t gddr6_mr2; // gddr6 mode register2 value 3414 uint16_t gddr6_mr4; // gddr6 mode register4 value 3415 uint16_t gddr6_mr7; // gddr6 mode register7 value 3416 uint16_t gddr6_mr8; // gddr6 mode register8 value 3417 char dram_pnstring[40]; // part number end with '0'. 3418 }; 3419 3420 struct atom_gddr6_ac_timing_v2_5 { 3421 uint32_t u32umc_id_access; 3422 uint8_t RL; 3423 uint8_t WL; 3424 uint8_t tRAS; 3425 uint8_t tRC; 3426 3427 uint16_t tREFI; 3428 uint8_t tRFC; 3429 uint8_t tRFCpb; 3430 3431 uint8_t tRREFD; 3432 uint8_t tRCDRD; 3433 uint8_t tRCDWR; 3434 uint8_t tRP; 3435 3436 uint8_t tRRDS; 3437 uint8_t tRRDL; 3438 uint8_t tWR; 3439 uint8_t tWTRS; 3440 3441 uint8_t tWTRL; 3442 uint8_t tFAW; 3443 uint8_t tCCDS; 3444 uint8_t tCCDL; 3445 3446 uint8_t tCRCRL; 3447 uint8_t tCRCWL; 3448 uint8_t tCKE; 3449 uint8_t tCKSRE; 3450 3451 uint8_t tCKSRX; 3452 uint8_t tRTPS; 3453 uint8_t tRTPL; 3454 uint8_t tMRD; 3455 3456 uint8_t tMOD; 3457 uint8_t tXS; 3458 uint8_t tXHP; 3459 uint8_t tXSMRS; 3460 3461 uint32_t tXSH; 3462 3463 uint8_t tPD; 3464 uint8_t tXP; 3465 uint8_t tCPDED; 3466 uint8_t tACTPDE; 3467 3468 uint8_t tPREPDE; 3469 uint8_t tREFPDE; 3470 uint8_t tMRSPDEN; 3471 uint8_t tRDSRE; 3472 3473 uint8_t tWRSRE; 3474 uint8_t tPPD; 3475 uint8_t tCCDMW; 3476 uint8_t tWTRTR; 3477 3478 uint8_t tLTLTR; 3479 uint8_t tREFTR; 3480 uint8_t VNDR; 3481 uint8_t reserved[9]; 3482 }; 3483 3484 struct atom_gddr6_bit_byte_remap { 3485 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap 3486 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0 3487 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1 3488 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2 3489 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0 3490 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1 3491 uint32_t phy_dram; //mmUMC_PHY_DRAM 3492 }; 3493 3494 struct atom_gddr6_dram_data_remap { 3495 uint32_t table_size; 3496 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK 3497 struct atom_gddr6_bit_byte_remap bit_byte_remap[16]; 3498 }; 3499 3500 struct atom_vram_info_header_v2_5 { 3501 struct atom_common_table_header table_header; 3502 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings 3503 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings 3504 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3505 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3506 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping 3507 uint16_t reserved; // offset of reserved 3508 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3509 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings 3510 uint8_t vram_module_num; // indicate number of VRAM module 3511 uint8_t umcip_min_ver; 3512 uint8_t umcip_max_ver; 3513 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3514 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3515 }; 3516 3517 struct atom_vram_info_header_v2_6 { 3518 struct atom_common_table_header table_header; 3519 uint16_t mem_adjust_tbloffset; 3520 uint16_t mem_clk_patch_tbloffset; 3521 uint16_t mc_adjust_pertile_tbloffset; 3522 uint16_t mc_phyinit_tbloffset; 3523 uint16_t dram_data_remap_tbloffset; 3524 uint16_t tmrs_seq_offset; 3525 uint16_t post_ucode_init_offset; 3526 uint16_t vram_rsd2; 3527 uint8_t vram_module_num; 3528 uint8_t umcip_min_ver; 3529 uint8_t umcip_max_ver; 3530 uint8_t mc_phy_tile_num; 3531 struct atom_vram_module_v9 vram_module[16]; 3532 }; 3533 /* 3534 *************************************************************************** 3535 Data Table voltageobject_info structure 3536 *************************************************************************** 3537 */ 3538 struct atom_i2c_data_entry 3539 { 3540 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 3541 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 3542 }; 3543 3544 struct atom_voltage_object_header_v4{ 3545 uint8_t voltage_type; //enum atom_voltage_type 3546 uint8_t voltage_mode; //enum atom_voltage_object_mode 3547 uint16_t object_size; //Size of Object 3548 }; 3549 3550 // atom_voltage_object_header_v4.voltage_mode 3551 enum atom_voltage_object_mode 3552 { 3553 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 3554 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequence through I2C -> atom_i2c_voltage_object_v4 3555 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 3556 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 3557 VOLTAGE_OBJ_EVV = 8, 3558 VOLTAGE_OBJ_MERGED_POWER = 9, 3559 }; 3560 3561 struct atom_i2c_voltage_object_v4 3562 { 3563 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3564 uint8_t regulator_id; //Indicate Voltage Regulator Id 3565 uint8_t i2c_id; 3566 uint8_t i2c_slave_addr; 3567 uint8_t i2c_control_offset; 3568 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 3569 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 3570 uint8_t reserved[2]; 3571 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 3572 }; 3573 3574 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 3575 enum atom_i2c_voltage_control_flag 3576 { 3577 VOLTAGE_DATA_ONE_BYTE = 0, 3578 VOLTAGE_DATA_TWO_BYTE = 1, 3579 }; 3580 3581 3582 struct atom_voltage_gpio_map_lut 3583 { 3584 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 3585 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 3586 }; 3587 3588 struct atom_gpio_voltage_object_v4 3589 { 3590 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 3591 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 3592 uint8_t gpio_entry_num; // indicate the entry numbers of Votlage/Gpio value Look up table 3593 uint8_t phase_delay_us; // phase delay in unit of micro second 3594 uint8_t reserved; 3595 uint32_t gpio_mask_val; // GPIO Mask value 3596 struct atom_voltage_gpio_map_lut voltage_gpio_lut[] __counted_by(gpio_entry_num); 3597 }; 3598 3599 struct atom_svid2_voltage_object_v4 3600 { 3601 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 3602 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 3603 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 3604 uint8_t psi0_enable; // 3605 uint8_t maxvstep; 3606 uint8_t telemetry_offset; 3607 uint8_t telemetry_gain; 3608 uint16_t reserved1; 3609 }; 3610 3611 struct atom_merged_voltage_object_v4 3612 { 3613 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 3614 uint8_t merged_powerrail_type; //enum atom_voltage_type 3615 uint8_t reserved[3]; 3616 }; 3617 3618 union atom_voltage_object_v4{ 3619 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 3620 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 3621 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 3622 struct atom_merged_voltage_object_v4 merged_voltage_obj; 3623 }; 3624 3625 struct atom_voltage_objects_info_v4_1 3626 { 3627 struct atom_common_table_header table_header; 3628 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 3629 }; 3630 3631 3632 /* 3633 *************************************************************************** 3634 All Command Function structure definition 3635 *************************************************************************** 3636 */ 3637 3638 /* 3639 *************************************************************************** 3640 Structures used by asic_init 3641 *************************************************************************** 3642 */ 3643 3644 struct asic_init_engine_parameters 3645 { 3646 uint32_t sclkfreqin10khz:24; 3647 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 3648 }; 3649 3650 struct asic_init_mem_parameters 3651 { 3652 uint32_t mclkfreqin10khz:24; 3653 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 3654 }; 3655 3656 struct asic_init_parameters_v2_1 3657 { 3658 struct asic_init_engine_parameters engineparam; 3659 struct asic_init_mem_parameters memparam; 3660 }; 3661 3662 struct asic_init_ps_allocation_v2_1 3663 { 3664 struct asic_init_parameters_v2_1 param; 3665 uint32_t reserved[16]; 3666 }; 3667 3668 3669 enum atom_asic_init_engine_flag 3670 { 3671 b3NORMAL_ENGINE_INIT = 0, 3672 b3SRIOV_SKIP_ASIC_INIT = 0x02, 3673 b3SRIOV_LOAD_UCODE = 0x40, 3674 }; 3675 3676 enum atom_asic_init_mem_flag 3677 { 3678 b3NORMAL_MEM_INIT = 0, 3679 b3DRAM_SELF_REFRESH_EXIT =0x20, 3680 }; 3681 3682 /* 3683 *************************************************************************** 3684 Structures used by setengineclock 3685 *************************************************************************** 3686 */ 3687 3688 struct set_engine_clock_parameters_v2_1 3689 { 3690 uint32_t sclkfreqin10khz:24; 3691 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3692 uint32_t reserved[10]; 3693 }; 3694 3695 struct set_engine_clock_ps_allocation_v2_1 3696 { 3697 struct set_engine_clock_parameters_v2_1 clockinfo; 3698 uint32_t reserved[10]; 3699 }; 3700 3701 3702 enum atom_set_engine_mem_clock_flag 3703 { 3704 b3NORMAL_CHANGE_CLOCK = 0, 3705 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 3706 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 3707 }; 3708 3709 /* 3710 *************************************************************************** 3711 Structures used by getengineclock 3712 *************************************************************************** 3713 */ 3714 struct get_engine_clock_parameter 3715 { 3716 uint32_t sclk_10khz; // current engine speed in 10KHz unit 3717 uint32_t reserved; 3718 }; 3719 3720 /* 3721 *************************************************************************** 3722 Structures used by setmemoryclock 3723 *************************************************************************** 3724 */ 3725 struct set_memory_clock_parameters_v2_1 3726 { 3727 uint32_t mclkfreqin10khz:24; 3728 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3729 uint32_t reserved[10]; 3730 }; 3731 3732 struct set_memory_clock_ps_allocation_v2_1 3733 { 3734 struct set_memory_clock_parameters_v2_1 clockinfo; 3735 uint32_t reserved[10]; 3736 }; 3737 3738 3739 /* 3740 *************************************************************************** 3741 Structures used by getmemoryclock 3742 *************************************************************************** 3743 */ 3744 struct get_memory_clock_parameter 3745 { 3746 uint32_t mclk_10khz; // current engine speed in 10KHz unit 3747 uint32_t reserved; 3748 }; 3749 3750 3751 3752 /* 3753 *************************************************************************** 3754 Structures used by setvoltage 3755 *************************************************************************** 3756 */ 3757 3758 struct set_voltage_parameters_v1_4 3759 { 3760 uint8_t voltagetype; /* enum atom_voltage_type */ 3761 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 3762 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 3763 }; 3764 3765 //set_voltage_parameters_v2_1.voltagemode 3766 enum atom_set_voltage_command{ 3767 ATOM_SET_VOLTAGE = 0, 3768 ATOM_INIT_VOLTAGE_REGULATOR = 3, 3769 ATOM_SET_VOLTAGE_PHASE = 4, 3770 ATOM_GET_LEAKAGE_ID = 8, 3771 }; 3772 3773 struct set_voltage_ps_allocation_v1_4 3774 { 3775 struct set_voltage_parameters_v1_4 setvoltageparam; 3776 uint32_t reserved[10]; 3777 }; 3778 3779 3780 /* 3781 *************************************************************************** 3782 Structures used by computegpuclockparam 3783 *************************************************************************** 3784 */ 3785 3786 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 3787 enum atom_gpu_clock_type 3788 { 3789 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 3790 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 3791 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 3792 }; 3793 3794 struct compute_gpu_clock_input_parameter_v1_8 3795 { 3796 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3797 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 3798 uint32_t reserved[5]; 3799 }; 3800 3801 3802 struct compute_gpu_clock_output_parameter_v1_8 3803 { 3804 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3805 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 3806 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 3807 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 3808 uint16_t pll_ss_slew_frac; 3809 uint8_t pll_ss_enable; 3810 uint8_t reserved; 3811 uint32_t reserved1[2]; 3812 }; 3813 3814 3815 3816 /* 3817 *************************************************************************** 3818 Structures used by ReadEfuseValue 3819 *************************************************************************** 3820 */ 3821 3822 struct read_efuse_input_parameters_v3_1 3823 { 3824 uint16_t efuse_start_index; 3825 uint8_t reserved; 3826 uint8_t bitslen; 3827 }; 3828 3829 // ReadEfuseValue input/output parameter 3830 union read_efuse_value_parameters_v3_1 3831 { 3832 struct read_efuse_input_parameters_v3_1 efuse_info; 3833 uint32_t efusevalue; 3834 }; 3835 3836 3837 /* 3838 *************************************************************************** 3839 Structures used by getsmuclockinfo 3840 *************************************************************************** 3841 */ 3842 struct atom_get_smu_clock_info_parameters_v3_1 3843 { 3844 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 3845 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3846 uint8_t command; // enum of atom_get_smu_clock_info_command 3847 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3848 }; 3849 3850 enum atom_get_smu_clock_info_command 3851 { 3852 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 3853 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 3854 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 3855 }; 3856 3857 enum atom_smu9_syspll0_clock_id 3858 { 3859 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 3860 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 3861 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3862 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3863 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 3864 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 3865 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 3866 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 3867 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 3868 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 3869 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 3870 }; 3871 3872 enum atom_smu11_syspll_id { 3873 SMU11_SYSPLL0_ID = 0, 3874 SMU11_SYSPLL1_0_ID = 1, 3875 SMU11_SYSPLL1_1_ID = 2, 3876 SMU11_SYSPLL1_2_ID = 3, 3877 SMU11_SYSPLL2_ID = 4, 3878 SMU11_SYSPLL3_0_ID = 5, 3879 SMU11_SYSPLL3_1_ID = 6, 3880 }; 3881 3882 enum atom_smu11_syspll0_clock_id { 3883 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 3884 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3885 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3886 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 3887 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 3888 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 3889 }; 3890 3891 enum atom_smu11_syspll1_0_clock_id { 3892 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 3893 }; 3894 3895 enum atom_smu11_syspll1_1_clock_id { 3896 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 3897 }; 3898 3899 enum atom_smu11_syspll1_2_clock_id { 3900 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 3901 }; 3902 3903 enum atom_smu11_syspll2_clock_id { 3904 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 3905 }; 3906 3907 enum atom_smu11_syspll3_0_clock_id { 3908 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 3909 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 3910 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 3911 }; 3912 3913 enum atom_smu11_syspll3_1_clock_id { 3914 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 3915 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 3916 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 3917 }; 3918 3919 enum atom_smu12_syspll_id { 3920 SMU12_SYSPLL0_ID = 0, 3921 SMU12_SYSPLL1_ID = 1, 3922 SMU12_SYSPLL2_ID = 2, 3923 SMU12_SYSPLL3_0_ID = 3, 3924 SMU12_SYSPLL3_1_ID = 4, 3925 }; 3926 3927 enum atom_smu12_syspll0_clock_id { 3928 SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK 3929 SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3930 SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3931 SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3932 SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK 3933 SMU12_SYSPLL0_VCLK_ID = 5, // VCLK 3934 SMU12_SYSPLL0_LCLK_ID = 6, // LCLK 3935 SMU12_SYSPLL0_DCLK_ID = 7, // DCLK 3936 SMU12_SYSPLL0_ACLK_ID = 8, // ACLK 3937 SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK 3938 SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK 3939 }; 3940 3941 enum atom_smu12_syspll1_clock_id { 3942 SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK 3943 SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK 3944 SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK 3945 SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK 3946 }; 3947 3948 enum atom_smu12_syspll2_clock_id { 3949 SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK 3950 }; 3951 3952 enum atom_smu12_syspll3_0_clock_id { 3953 SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK 3954 }; 3955 3956 enum atom_smu12_syspll3_1_clock_id { 3957 SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK 3958 }; 3959 3960 struct atom_get_smu_clock_info_output_parameters_v3_1 3961 { 3962 union { 3963 uint32_t smu_clock_freq_hz; 3964 uint32_t syspllvcofreq_10khz; 3965 uint32_t sysspllrefclk_10khz; 3966 }atom_smu_outputclkfreq; 3967 }; 3968 3969 3970 3971 /* 3972 *************************************************************************** 3973 Structures used by dynamicmemorysettings 3974 *************************************************************************** 3975 */ 3976 3977 enum atom_dynamic_memory_setting_command 3978 { 3979 COMPUTE_MEMORY_PLL_PARAM = 1, 3980 COMPUTE_ENGINE_PLL_PARAM = 2, 3981 ADJUST_MC_SETTING_PARAM = 3, 3982 }; 3983 3984 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 3985 struct dynamic_mclk_settings_parameters_v2_1 3986 { 3987 uint32_t mclk_10khz:24; //Input= target mclk 3988 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3989 uint32_t reserved; 3990 }; 3991 3992 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 3993 struct dynamic_sclk_settings_parameters_v2_1 3994 { 3995 uint32_t sclk_10khz:24; //Input= target mclk 3996 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3997 uint32_t mclk_10khz; 3998 uint32_t reserved; 3999 }; 4000 4001 union dynamic_memory_settings_parameters_v2_1 4002 { 4003 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 4004 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 4005 }; 4006 4007 4008 4009 /* 4010 *************************************************************************** 4011 Structures used by memorytraining 4012 *************************************************************************** 4013 */ 4014 4015 enum atom_umc6_0_ucode_function_call_enum_id 4016 { 4017 UMC60_UCODE_FUNC_ID_REINIT = 0, 4018 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 4019 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 4020 }; 4021 4022 4023 struct memory_training_parameters_v2_1 4024 { 4025 uint8_t ucode_func_id; 4026 uint8_t ucode_reserved[3]; 4027 uint32_t reserved[5]; 4028 }; 4029 4030 4031 /* 4032 *************************************************************************** 4033 Structures used by setpixelclock 4034 *************************************************************************** 4035 */ 4036 4037 struct set_pixel_clock_parameter_v1_7 4038 { 4039 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 4040 4041 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 4042 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 4043 // indicate which graphic encoder will be used. 4044 uint8_t encoder_mode; // Encoder mode: 4045 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 4046 uint8_t crtc_id; // enum of atom_crtc_def 4047 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 4048 uint8_t reserved1[2]; 4049 uint32_t reserved2; 4050 }; 4051 4052 //ucMiscInfo 4053 enum atom_set_pixel_clock_v1_7_misc_info 4054 { 4055 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 4056 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 4057 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 4058 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 4059 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 4060 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 4061 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 4062 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 4063 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 4064 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 4065 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 4066 }; 4067 4068 /* deep_color_ratio */ 4069 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 4070 { 4071 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 4072 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 4073 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 4074 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 4075 }; 4076 4077 /* 4078 *************************************************************************** 4079 Structures used by setdceclock 4080 *************************************************************************** 4081 */ 4082 4083 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 4084 struct set_dce_clock_parameters_v2_1 4085 { 4086 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 4087 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 4088 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 4089 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 4090 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 4091 }; 4092 4093 //ucDCEClkType 4094 enum atom_set_dce_clock_clock_type 4095 { 4096 DCE_CLOCK_TYPE_DISPCLK = 0, 4097 DCE_CLOCK_TYPE_DPREFCLK = 1, 4098 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 4099 }; 4100 4101 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 4102 enum atom_set_dce_clock_dprefclk_flag 4103 { 4104 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 4105 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 4106 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 4107 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 4108 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 4109 }; 4110 4111 //ucDCEClkFlag when ucDCEClkType == PIXCLK 4112 enum atom_set_dce_clock_pixclk_flag 4113 { 4114 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 4115 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 4116 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 4117 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 4118 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 4119 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 4120 }; 4121 4122 struct set_dce_clock_ps_allocation_v2_1 4123 { 4124 struct set_dce_clock_parameters_v2_1 param; 4125 uint32_t ulReserved[2]; 4126 }; 4127 4128 4129 /****************************************************************************/ 4130 // Structures used by BlankCRTC 4131 /****************************************************************************/ 4132 struct blank_crtc_parameters 4133 { 4134 uint8_t crtc_id; // enum atom_crtc_def 4135 uint8_t blanking; // enum atom_blank_crtc_command 4136 uint16_t reserved; 4137 uint32_t reserved1; 4138 }; 4139 4140 enum atom_blank_crtc_command 4141 { 4142 ATOM_BLANKING = 1, 4143 ATOM_BLANKING_OFF = 0, 4144 }; 4145 4146 /****************************************************************************/ 4147 // Structures used by enablecrtc 4148 /****************************************************************************/ 4149 struct enable_crtc_parameters 4150 { 4151 uint8_t crtc_id; // enum atom_crtc_def 4152 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 4153 uint8_t padding[2]; 4154 }; 4155 4156 4157 /****************************************************************************/ 4158 // Structure used by EnableDispPowerGating 4159 /****************************************************************************/ 4160 struct enable_disp_power_gating_parameters_v2_1 4161 { 4162 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 4163 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 4164 uint8_t padding[2]; 4165 }; 4166 4167 struct enable_disp_power_gating_ps_allocation 4168 { 4169 struct enable_disp_power_gating_parameters_v2_1 param; 4170 uint32_t ulReserved[4]; 4171 }; 4172 4173 /****************************************************************************/ 4174 // Structure used in setcrtc_usingdtdtiming 4175 /****************************************************************************/ 4176 struct set_crtc_using_dtd_timing_parameters 4177 { 4178 uint16_t h_size; 4179 uint16_t h_blanking_time; 4180 uint16_t v_size; 4181 uint16_t v_blanking_time; 4182 uint16_t h_syncoffset; 4183 uint16_t h_syncwidth; 4184 uint16_t v_syncoffset; 4185 uint16_t v_syncwidth; 4186 uint16_t modemiscinfo; 4187 uint8_t h_border; 4188 uint8_t v_border; 4189 uint8_t crtc_id; // enum atom_crtc_def 4190 uint8_t encoder_mode; // atom_encode_mode_def 4191 uint8_t padding[2]; 4192 }; 4193 4194 4195 /****************************************************************************/ 4196 // Structures used by processi2cchanneltransaction 4197 /****************************************************************************/ 4198 struct process_i2c_channel_transaction_parameters 4199 { 4200 uint8_t i2cspeed_khz; 4201 union { 4202 uint8_t regindex; 4203 uint8_t status; /* enum atom_process_i2c_flag */ 4204 } regind_status; 4205 uint16_t i2c_data_out; 4206 uint8_t flag; /* enum atom_process_i2c_status */ 4207 uint8_t trans_bytes; 4208 uint8_t slave_addr; 4209 uint8_t i2c_id; 4210 }; 4211 4212 //ucFlag 4213 enum atom_process_i2c_flag 4214 { 4215 HW_I2C_WRITE = 1, 4216 HW_I2C_READ = 0, 4217 I2C_2BYTE_ADDR = 0x02, 4218 HW_I2C_SMBUS_BYTE_WR = 0x04, 4219 }; 4220 4221 //status 4222 enum atom_process_i2c_status 4223 { 4224 HW_ASSISTED_I2C_STATUS_FAILURE =2, 4225 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 4226 }; 4227 4228 4229 /****************************************************************************/ 4230 // Structures used by processauxchanneltransaction 4231 /****************************************************************************/ 4232 4233 struct process_aux_channel_transaction_parameters_v1_2 4234 { 4235 uint16_t aux_request; 4236 uint16_t dataout; 4237 uint8_t channelid; 4238 union { 4239 uint8_t reply_status; 4240 uint8_t aux_delay; 4241 } aux_status_delay; 4242 uint8_t dataout_len; 4243 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 4244 }; 4245 4246 4247 /****************************************************************************/ 4248 // Structures used by selectcrtc_source 4249 /****************************************************************************/ 4250 4251 struct select_crtc_source_parameters_v2_3 4252 { 4253 uint8_t crtc_id; // enum atom_crtc_def 4254 uint8_t encoder_id; // enum atom_dig_def 4255 uint8_t encode_mode; // enum atom_encode_mode_def 4256 uint8_t dst_bpc; // enum atom_panel_bit_per_color 4257 }; 4258 4259 4260 /****************************************************************************/ 4261 // Structures used by digxencodercontrol 4262 /****************************************************************************/ 4263 4264 // ucAction: 4265 enum atom_dig_encoder_control_action 4266 { 4267 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 4268 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 4269 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 4270 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 4271 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 4272 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 4273 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 4274 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 4275 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 4276 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 4277 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 4278 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 4279 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 4280 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 4281 }; 4282 4283 //define ucPanelMode 4284 enum atom_dig_encoder_control_panelmode 4285 { 4286 DP_PANEL_MODE_DISABLE = 0x00, 4287 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 4288 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 4289 }; 4290 4291 //ucDigId 4292 enum atom_dig_encoder_control_v5_digid 4293 { 4294 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 4295 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 4296 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 4297 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 4298 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 4299 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 4300 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 4301 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 4302 }; 4303 4304 struct dig_encoder_stream_setup_parameters_v1_5 4305 { 4306 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4307 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 4308 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 4309 uint8_t lanenum; // Lane number 4310 uint32_t pclk_10khz; // Pixel Clock in 10Khz 4311 uint8_t bitpercolor; 4312 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 4313 uint8_t reserved[2]; 4314 }; 4315 4316 struct dig_encoder_link_setup_parameters_v1_5 4317 { 4318 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4319 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 4320 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 4321 uint8_t lanenum; // Lane number 4322 uint8_t symclk_10khz; // Symbol Clock in 10Khz 4323 uint8_t hpd_sel; 4324 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 4325 uint8_t reserved[2]; 4326 }; 4327 4328 struct dp_panel_mode_set_parameters_v1_5 4329 { 4330 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4331 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 4332 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 4333 uint8_t reserved1; 4334 uint32_t reserved2[2]; 4335 }; 4336 4337 struct dig_encoder_generic_cmd_parameters_v1_5 4338 { 4339 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4340 uint8_t action; // = rest of generic encoder command which does not carry any parameters 4341 uint8_t reserved1[2]; 4342 uint32_t reserved2[2]; 4343 }; 4344 4345 union dig_encoder_control_parameters_v1_5 4346 { 4347 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 4348 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 4349 struct dig_encoder_link_setup_parameters_v1_5 link_param; 4350 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 4351 }; 4352 4353 /* 4354 *************************************************************************** 4355 Structures used by dig1transmittercontrol 4356 *************************************************************************** 4357 */ 4358 struct dig_transmitter_control_parameters_v1_6 4359 { 4360 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 4361 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 4362 union { 4363 uint8_t digmode; // enum atom_encode_mode_def 4364 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 4365 } mode_laneset; 4366 uint8_t lanenum; // Lane number 1, 2, 4, 8 4367 uint32_t symclk_10khz; // Symbol Clock in 10Khz 4368 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 4369 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 4370 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 4371 uint8_t reserved; 4372 uint32_t reserved1; 4373 }; 4374 4375 struct dig_transmitter_control_ps_allocation_v1_6 4376 { 4377 struct dig_transmitter_control_parameters_v1_6 param; 4378 uint32_t reserved[4]; 4379 }; 4380 4381 //ucAction 4382 enum atom_dig_transmitter_control_action 4383 { 4384 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 4385 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 4386 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 4387 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 4388 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 4389 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 4390 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 4391 ATOM_TRANSMITTER_ACTION_INIT = 7, 4392 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 4393 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 4394 ATOM_TRANSMITTER_ACTION_SETUP = 10, 4395 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 4396 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 4397 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 4398 }; 4399 4400 // digfe_sel 4401 enum atom_dig_transmitter_control_digfe_sel 4402 { 4403 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 4404 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 4405 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 4406 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 4407 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 4408 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 4409 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 4410 }; 4411 4412 4413 //ucHPDSel 4414 enum atom_dig_transmitter_control_hpd_sel 4415 { 4416 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 4417 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 4418 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 4419 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 4420 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 4421 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 4422 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 4423 }; 4424 4425 // ucDPLaneSet 4426 enum atom_dig_transmitter_control_dplaneset 4427 { 4428 DP_LANE_SET__0DB_0_4V = 0x00, 4429 DP_LANE_SET__0DB_0_6V = 0x01, 4430 DP_LANE_SET__0DB_0_8V = 0x02, 4431 DP_LANE_SET__0DB_1_2V = 0x03, 4432 DP_LANE_SET__3_5DB_0_4V = 0x08, 4433 DP_LANE_SET__3_5DB_0_6V = 0x09, 4434 DP_LANE_SET__3_5DB_0_8V = 0x0a, 4435 DP_LANE_SET__6DB_0_4V = 0x10, 4436 DP_LANE_SET__6DB_0_6V = 0x11, 4437 DP_LANE_SET__9_5DB_0_4V = 0x18, 4438 }; 4439 4440 4441 4442 /****************************************************************************/ 4443 // Structures used by ExternalEncoderControl V2.4 4444 /****************************************************************************/ 4445 4446 struct external_encoder_control_parameters_v2_4 4447 { 4448 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 4449 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 4450 uint8_t action; // 4451 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 4452 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 4453 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 4454 uint8_t hpd_id; 4455 }; 4456 4457 4458 // ucAction 4459 enum external_encoder_control_action_def 4460 { 4461 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 4462 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 4463 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 4464 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 4465 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 4466 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 4467 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 4468 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 4469 }; 4470 4471 // ucConfig 4472 enum external_encoder_control_v2_4_config_def 4473 { 4474 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 4475 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 4476 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 4477 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 4478 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 4479 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 4480 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 4481 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 4482 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 4483 }; 4484 4485 struct external_encoder_control_ps_allocation_v2_4 4486 { 4487 struct external_encoder_control_parameters_v2_4 sExtEncoder; 4488 uint32_t reserved[2]; 4489 }; 4490 4491 4492 /* 4493 *************************************************************************** 4494 AMD ACPI Table 4495 4496 *************************************************************************** 4497 */ 4498 4499 struct amd_acpi_description_header{ 4500 uint32_t signature; 4501 uint32_t tableLength; //Length 4502 uint8_t revision; 4503 uint8_t checksum; 4504 uint8_t oemId[6]; 4505 uint8_t oemTableId[8]; //UINT64 OemTableId; 4506 uint32_t oemRevision; 4507 uint32_t creatorId; 4508 uint32_t creatorRevision; 4509 }; 4510 4511 struct uefi_acpi_vfct{ 4512 struct amd_acpi_description_header sheader; 4513 uint8_t tableUUID[16]; //0x24 4514 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure. 4515 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure. 4516 uint32_t reserved[4]; //0x3C 4517 }; 4518 4519 struct vfct_image_header{ 4520 uint32_t pcibus; //0x4C 4521 uint32_t pcidevice; //0x50 4522 uint32_t pcifunction; //0x54 4523 uint16_t vendorid; //0x58 4524 uint16_t deviceid; //0x5A 4525 uint16_t ssvid; //0x5C 4526 uint16_t ssid; //0x5E 4527 uint32_t revision; //0x60 4528 uint32_t imagelength; //0x64 4529 }; 4530 4531 4532 struct gop_vbios_content { 4533 struct vfct_image_header vbiosheader; 4534 uint8_t vbioscontent[1]; 4535 }; 4536 4537 struct gop_lib1_content { 4538 struct vfct_image_header lib1header; 4539 uint8_t lib1content[1]; 4540 }; 4541 4542 4543 4544 /* 4545 *************************************************************************** 4546 Scratch Register definitions 4547 Each number below indicates which scratch register request, Active and 4548 Connect all share the same definitions as display_device_tag defines 4549 *************************************************************************** 4550 */ 4551 4552 enum scratch_register_def{ 4553 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 4554 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 4555 ATOM_ACTIVE_INFO_DEF = 3, 4556 ATOM_LCD_INFO_DEF = 4, 4557 ATOM_DEVICE_REQ_INFO_DEF = 5, 4558 ATOM_ACC_CHANGE_INFO_DEF = 6, 4559 ATOM_PRE_OS_MODE_INFO_DEF = 7, 4560 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 4561 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 4562 }; 4563 4564 enum scratch_device_connect_info_bit_def{ 4565 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 4566 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 4567 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 4568 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 4569 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 4570 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 4571 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 4572 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 4573 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 4574 }; 4575 4576 enum scratch_bl_bri_level_info_bit_def{ 4577 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 4578 #ifndef _H2INC 4579 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 4580 ATOM_DEVICE_DPMS_STATE =0x00010000, 4581 #endif 4582 }; 4583 4584 enum scratch_active_info_bits_def{ 4585 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 4586 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 4587 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 4588 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 4589 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 4590 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 4591 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 4592 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 4593 }; 4594 4595 enum scratch_device_req_info_bits_def{ 4596 ATOM_DISPLAY_LCD1_REQ =0x0002, 4597 ATOM_DISPLAY_DFP1_REQ =0x0008, 4598 ATOM_DISPLAY_DFP2_REQ =0x0080, 4599 ATOM_DISPLAY_DFP3_REQ =0x0200, 4600 ATOM_DISPLAY_DFP4_REQ =0x0400, 4601 ATOM_DISPLAY_DFP5_REQ =0x0800, 4602 ATOM_DISPLAY_DFP6_REQ =0x0040, 4603 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 4604 }; 4605 4606 enum scratch_acc_change_info_bitshift_def{ 4607 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 4608 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 4609 }; 4610 4611 enum scratch_acc_change_info_bits_def{ 4612 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 4613 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 4614 }; 4615 4616 enum scratch_pre_os_mode_info_bits_def{ 4617 ATOM_PRE_OS_MODE_MASK =0x00000003, 4618 ATOM_PRE_OS_MODE_VGA =0x00000000, 4619 ATOM_PRE_OS_MODE_VESA =0x00000001, 4620 ATOM_PRE_OS_MODE_GOP =0x00000002, 4621 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 4622 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 4623 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 4624 ATOM_ASIC_INIT_COMPLETE =0x00000200, 4625 #ifndef _H2INC 4626 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 4627 #endif 4628 }; 4629 4630 4631 4632 /* 4633 *************************************************************************** 4634 ATOM firmware ID header file 4635 !! Please keep it at end of the atomfirmware.h !! 4636 *************************************************************************** 4637 */ 4638 #include "atomfirmwareid.h" 4639 #pragma pack() 4640 4641 #endif 4642 4643