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/linux/include/linux/
H A Dsizes.h54 #define SZ_4G _AC(0x100000000, ULL)
55 #define SZ_8G _AC(0x200000000, ULL)
56 #define SZ_16G _AC(0x400000000, ULL)
57 #define SZ_32G _AC(0x800000000, ULL)
58 #define SZ_64G _AC(0x1000000000, ULL)
59 #define SZ_128G _AC(0x2000000000, ULL)
60 #define SZ_256G _AC(0x4000000000, ULL)
61 #define SZ_512G _AC(0x8000000000, ULL)
63 #define SZ_1T _AC(0x10000000000, ULL)
64 #define SZ_2T _AC(0x20000000000, ULL)
[all …]
H A Drseq_entry.h327 unsafe_put_user(0ULL, &t->rseq.usrptr->rseq_cs, efault); in rseq_debug_update_user_cs()
332 unsafe_put_user(0ULL, &t->rseq.usrptr->rseq_cs, efault); in rseq_debug_update_user_cs()
334 abort_ip = 0ULL; in rseq_debug_update_user_cs()
449 unsafe_put_user(0ULL, &t->rseq.usrptr->rseq_cs, efault); in rseq_update_user_cs()
455 unsafe_put_user(0ULL, &t->rseq.usrptr->rseq_cs, efault); in rseq_update_user_cs()
457 abort_ip = 0ULL; in rseq_update_user_cs()
/linux/arch/powerpc/platforms/powernv/
H A Dvas-window.c220 write_hvwc_reg(window, VREG(LPID), 0ULL); in reset_window_regs()
221 write_hvwc_reg(window, VREG(PID), 0ULL); in reset_window_regs()
222 write_hvwc_reg(window, VREG(XLATE_MSR), 0ULL); in reset_window_regs()
223 write_hvwc_reg(window, VREG(XLATE_LPCR), 0ULL); in reset_window_regs()
224 write_hvwc_reg(window, VREG(XLATE_CTL), 0ULL); in reset_window_regs()
225 write_hvwc_reg(window, VREG(AMR), 0ULL); in reset_window_regs()
226 write_hvwc_reg(window, VREG(SEIDR), 0ULL); in reset_window_regs()
227 write_hvwc_reg(window, VREG(FAULT_TX_WIN), 0ULL); in reset_window_regs()
228 write_hvwc_reg(window, VREG(OSU_INTR_SRC_RA), 0ULL); in reset_window_regs()
229 write_hvwc_reg(window, VREG(HV_INTR_SRC_RA), 0ULL); in reset_window_regs()
[all …]
/linux/arch/parisc/include/asm/
H A Dpdc_chassis.h58 #define PDC_CHASSIS_LED_RUN_OFF (0ULL << 4)
62 #define PDC_CHASSIS_LED_ATTN_OFF (0ULL << 6)
65 #define PDC_CHASSIS_LED_FAULT_OFF (0ULL << 8)
160 #define PDC_CHASSIS_ALERT_FORWARD (0ULL << 36) /* no failure detected */
175 #define PDC_CHASSIS_SRC_NONE (0ULL << 28) /* unknown, no source stated */
192 #define PDC_CHASSIS_SRC_ID_UNSPEC (0ULL << 16)
195 #define PDC_CHASSIS_PB_D_PROC_NONE (0ULL << 32) /* no problem detail */
210 #define PDC_CHASSIS_ACT_STATUS_UNSPEC (0ULL << 0)
214 #define PDC_CHASSIS_CALL_SACT_UNSPEC (0ULL << 4) /* implementation dependent */
223 #define PDC_CHASSIS_REID_UNSPEC (0ULL << 44)
[all …]
/linux/drivers/gpu/drm/amd/ras/rascore/
H A Dras_umc_v12_0.h110 ((((pa >> UMC_V12_0_PA_SID0_BIT) & 0x1ULL) << 0ULL) | \
114 ((((pa >> UMC_V12_0_PA_B0_BIT) & 0x1ULL) << 0ULL) | \
120 ((((pa >> UMC_V12_0_PA_R0_BIT) & 0x1ULL) << 0ULL) | \
136 ((((pa >> UMC_V12_0_PA_C0_BIT) & 0x1ULL) << 0ULL) | \
143 ((((pa >> UMC_V12_0_PA_CH0_BIT) & 0x1ULL) << 0ULL) | \
151 #define UMC_V12_0_SOC_PA_TO_PC(pa) (((pa >> UMC_V12_0_PA_PC0_BIT) & 0x1ULL) << 0ULL)
154 ((((sid >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_SID0_BIT) | \
158 ((((bank >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_B0_BIT) | \
164 ((((row >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_R0_BIT) | \
180 ((((col >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_C0_BIT) | \
[all …]
/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_hal.c290 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
291 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
292 nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
294 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
295 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
376 nitrox_write_csr(ndev, offset, 0ULL); in nitrox_config_aqm_rings()
402 nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
403 nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
404 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
405 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-address.h300 #define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
324 #define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
330 #define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
331 #define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
332 #define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
334 #define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
335 #define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
339 #define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_devlink.c75 rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_intr_handler()
110 rvu_write64(rvu, blkaddr, NIX_AF_GEN_INT_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_gen_handler()
145 rvu_write64(rvu, blkaddr, NIX_AF_ERR_INT_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_err_handler()
180 rvu_write64(rvu, blkaddr, NIX_AF_RAS_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_ras_handler()
199 rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT_ENA_W1C, ~0ULL); in rvu_nix_unregister_interrupts()
200 rvu_write64(rvu, blkaddr, NIX_AF_GEN_INT_ENA_W1C, ~0ULL); in rvu_nix_unregister_interrupts()
201 rvu_write64(rvu, blkaddr, NIX_AF_ERR_INT_ENA_W1C, ~0ULL); in rvu_nix_unregister_interrupts()
202 rvu_write64(rvu, blkaddr, NIX_AF_RAS_ENA_W1C, ~0ULL); in rvu_nix_unregister_interrupts()
240 rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT_ENA_W1S, ~0ULL); in rvu_nix_register_interrupts()
248 rvu_write64(rvu, blkaddr, NIX_AF_GEN_INT_ENA_W1S, ~0ULL); in rvu_nix_register_interrupts()
[all …]
/linux/arch/x86/include/asm/
H A Dsegment.h14 ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \
15 (((flags) & _AC(0x0000f0ff,ULL)) << 40) | \
16 (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \
17 (((base) & _AC(0x00ffffff,ULL)) << 16) | \
18 (((limit) & _AC(0x0000ffff,ULL))))
H A Dpgtable-3level.h105 return pxx_xchg64(pte, ptep, 0ULL); in native_ptep_get_and_clear()
110 return pxx_xchg64(pmd, pmdp, 0ULL); in native_pmdp_get_and_clear()
115 return pxx_xchg64(pud, pudp, 0ULL); in native_pudp_get_and_clear()
H A Dmem_encrypt.h71 #define sme_me_mask 0ULL
72 #define sev_status 0ULL
/linux/include/asm-generic/
H A Ddiv64.h84 ___m = (~0ULL / ___b) * ___p; \
85 ___m += (((~0ULL % ___b + 1) * ___p) + ___b - 1) / ___b; \
88 ___x = ~0ULL / ___b * ___b - 1; \
109 ___m = (~0ULL / ___b) * ___p; \
110 ___m += ((~0ULL % ___b + 1) * ___p) / ___b; \
/linux/tools/include/linux/
H A Dbitfield.h85 __BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_MAX: "); \
98 __BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_FIT: "); \
112 __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
/linux/tools/perf/Documentation/
H A Dperf-dlfilter.txt231 PERF_DLFILTER_FLAG_BRANCH = 1ULL << 0,
232 PERF_DLFILTER_FLAG_CALL = 1ULL << 1,
233 PERF_DLFILTER_FLAG_RETURN = 1ULL << 2,
234 PERF_DLFILTER_FLAG_CONDITIONAL = 1ULL << 3,
235 PERF_DLFILTER_FLAG_SYSCALLRET = 1ULL << 4,
236 PERF_DLFILTER_FLAG_ASYNC = 1ULL << 5,
237 PERF_DLFILTER_FLAG_INTERRUPT = 1ULL << 6,
238 PERF_DLFILTER_FLAG_TX_ABORT = 1ULL << 7,
239 PERF_DLFILTER_FLAG_TRACE_BEGIN = 1ULL << 8,
240 PERF_DLFILTER_FLAG_TRACE_END = 1ULL << 9,
[all …]
/linux/drivers/spi/
H A Dspi-fsi.c134 *value = 0ULL; in fsi_spi_read_reg()
233 *out = 0ULL; in fsi_spi_data_out()
257 return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL); in fsi_spi_reset()
295 seq->data = 0ULL; in fsi_spi_sequence_init()
304 u64 status = 0ULL; in fsi_spi_transfer_data()
309 u64 out = 0ULL; in fsi_spi_transfer_data()
335 u64 in = 0ULL; in fsi_spi_transfer_data()
369 u64 clock_cfg = 0ULL; in fsi_spi_transfer_init()
370 u64 status = 0ULL; in fsi_spi_transfer_init()
405 rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL); in fsi_spi_transfer_init()
/linux/drivers/md/bcache/
H A Dbcache_ondisk.h13 { return (k->field >> offset) & ~(~0ULL << size); } \
17 k->field &= ~(~(~0ULL << size) << offset); \
18 k->field |= (v & ~(~0ULL << size)) << offset; \
34 { return (k->ptr[i] >> offset) & ~(~0ULL << size); } \
38 k->ptr[i] &= ~(~(~0ULL << size) << offset); \
39 k->ptr[i] |= (v & ~(~0ULL << size)) << offset; \
80 #define MAX_KEY_OFFSET (~0ULL >> 1)
/linux/drivers/of/
H A Dof_test.c127 .start = ULL(0x100000000),
130 .res_start = ULL(0x100000000),
131 .res_end = ULL(0x100000000),
138 .res_end = ULL(0x100000ffe),
/linux/arch/riscv/include/asm/
H A Dcsr.h215 #define ENVCFG_STCE (_AC(1, ULL) << 63)
216 #define ENVCFG_PBMTE (_AC(1, ULL) << 62)
217 #define ENVCFG_ADUE (_AC(1, ULL) << 61)
218 #define ENVCFG_PMM (_AC(0x3, ULL) << 32)
219 #define ENVCFG_PMM_PMLEN_0 (_AC(0x0, ULL) << 32)
220 #define ENVCFG_PMM_PMLEN_7 (_AC(0x2, ULL) << 32)
221 #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32)
/linux/include/vdso/
H A Dlimits.h14 #define LLONG_MAX ((long long)(~0ULL >> 1))
16 #define ULLONG_MAX (~0ULL)
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_cn9k.c83 u64 val = ULL(0); in cn93_vf_reset_iq()
108 u64 val = ULL(0); in cn93_vf_reset_oq()
203 u64 oq_ctl = ULL(0); in octep_vf_setup_oq_regs_cn93()
384 reg_val |= ULL(1); in octep_vf_enable_iq_cn93()
400 reg_val |= ULL(1); in octep_vf_enable_oq_cn93()
421 reg_val &= ~ULL(1); in octep_vf_disable_iq_cn93()
431 reg_val &= ~ULL(1); in octep_vf_disable_oq_cn93()
H A Doctep_vf_cnxk.c86 u64 val = ULL(0); in cnxk_vf_reset_iq()
110 u64 val = ULL(0); in cnxk_vf_reset_oq()
207 u64 oq_ctl = ULL(0); in octep_vf_setup_oq_regs_cnxk()
427 reg_val |= ULL(1); in octep_vf_enable_iq_cnxk()
443 reg_val |= ULL(1); in octep_vf_enable_oq_cnxk()
464 reg_val &= ~ULL(1); in octep_vf_disable_iq_cnxk()
474 reg_val &= ~ULL(1); in octep_vf_disable_oq_cnxk()
/linux/drivers/block/drbd/
H A Ddrbd_vli.h141 *out = ((in & ((~0ULL) >> (64-t))) >> b) + adj; \ in vli_decode_bits()
261 val &= ~0ULL >> (64 - bits); in bitstream_put_bits()
312 val &= ~0ULL >> (64 - bits); in bitstream_get_bits()
/linux/drivers/iommu/intel/
H A Dprq.c328 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); in intel_iommu_enable_prq()
329 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); in intel_iommu_enable_prq()
351 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); in intel_iommu_finish_prq()
352 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); in intel_iommu_finish_prq()
353 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); in intel_iommu_finish_prq()
/linux/drivers/net/ethernet/cavium/thunder/
H A Dnicvf_queues.h34 #define RBDR_SIZE0 0ULL /* 8K entries */
42 #define SND_QUEUE_SIZE0 0ULL /* 1K entries */
50 #define CMP_QUEUE_SIZE0 0ULL /* 1K entries */
114 #define RQ_DROP_RBDR_LVL 0ULL
/linux/fs/btrfs/
H A Dfs.h74 #define BTRFS_OLDEST_GENERATION 0ULL
286 #define BTRFS_FEATURE_COMPAT_SUPP 0ULL
287 #define BTRFS_FEATURE_COMPAT_SAFE_SET 0ULL
288 #define BTRFS_FEATURE_COMPAT_SAFE_CLEAR 0ULL
296 #define BTRFS_FEATURE_COMPAT_RO_SAFE_SET 0ULL
297 #define BTRFS_FEATURE_COMPAT_RO_SAFE_CLEAR 0ULL
335 #define BTRFS_FEATURE_INCOMPAT_SAFE_CLEAR 0ULL

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