Searched refs:TRCVMIDCVRn (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/hwtracing/coresight/ |
| H A D | coresight-etm4x.h | 92 #define TRCVMIDCVRn(n) (0x640 + (n * 8)) macro
470 CASE_##op((val), TRCVMIDCVRn(0)) \
471 CASE_##op((val), TRCVMIDCVRn(1)) \
472 CASE_##op((val), TRCVMIDCVRn(2)) \
473 CASE_##op((val), TRCVMIDCVRn(3)) \
474 CASE_##op((val), TRCVMIDCVRn(4)) \
475 CASE_##op((val), TRCVMIDCVRn(5)) \
476 CASE_##op((val), TRCVMIDCVRn(6)) \
477 CASE_##op((val), TRCVMIDCVRn(7)) \
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| H A D | coresight-etm4x-cfg.c | 92 } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) { in etm4_cfg_map_reg_offset()
98 CHECKREGIDX(TRCVMIDCVRn(0), vmid_val, idx, off_mask); in etm4_cfg_map_reg_offset()
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| H A D | coresight-etm4x-core.c | 588 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); in etm4_enable_hw()
1974 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); in __etm4_cpu_save()
2097 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); in __etm4_cpu_restore()
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