Home
last modified time | relevance | path

Searched refs:TO_CYCLES (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/mtd/nand/raw/
H A Ddavinci_nand.c820 #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP((ps) / 1000, (period_ns))) macro
837 cfg = TO_CYCLES(sdr->tCLR_min, cyc_ns) - 1; in davinci_nand_setup_interface()
840 cfg = max_t(s32, TO_CYCLES(sdr->tREA_max + MAX_TSU_PS, cyc_ns), in davinci_nand_setup_interface()
841 TO_CYCLES(sdr->tRP_min, cyc_ns)) - 1; in davinci_nand_setup_interface()
844 min = TO_CYCLES(sdr->tCEA_max + MAX_TSU_PS, cyc_ns) - 2; in davinci_nand_setup_interface()
848 cfg = TO_CYCLES((s32)(MAX_TH_PS - sdr->tCHZ_max), cyc_ns) - 1; in davinci_nand_setup_interface()
851 min = TO_CYCLES(sdr->tRC_min, cyc_ns) - 3; in davinci_nand_setup_interface()
855 cfg = TO_CYCLES((s32)(sdr->tRHZ_max - (timings.rhold + 1) * cyc_ns * 1000), cyc_ns); in davinci_nand_setup_interface()
856 cfg = max_t(s32, cfg, TO_CYCLES(sdr->tCHZ_max, cyc_ns)) - 1; in davinci_nand_setup_interface()
859 cfg = TO_CYCLES(sdr->tWP_min, cyc_ns) - 1; in davinci_nand_setup_interface()
[all …]
H A Dpl35x-nand-controller.c99 #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP((ps) / 1000, period_ns)) macro
815 val = TO_CYCLES(sdr->tRC_min, period_ns); in pl35x_nfc_setup_interface()
823 val = TO_CYCLES(sdr->tWC_min, period_ns); in pl35x_nfc_setup_interface()
834 val = TO_CYCLES(sdr->tWP_min, period_ns); in pl35x_nfc_setup_interface()
839 val = TO_CYCLES(sdr->tCLR_min, period_ns); in pl35x_nfc_setup_interface()
844 val = TO_CYCLES(sdr->tAR_min, period_ns); in pl35x_nfc_setup_interface()
849 val = TO_CYCLES(sdr->tRR_min, period_ns); in pl35x_nfc_setup_interface()
H A Dmarvell_nand.c473 #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns)) macro
2417 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1; in marvell_nfc_setup_interface()
2419 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1; in marvell_nfc_setup_interface()
2421 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns); in marvell_nfc_setup_interface()
2422 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1; in marvell_nfc_setup_interface()
2423 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns); in marvell_nfc_setup_interface()
2433 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns); in marvell_nfc_setup_interface()
2439 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
2441 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
2449 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); in marvell_nfc_setup_interface()
/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.c31 #define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period) macro
886 addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps); in gpmi_nfc_compute_timings()
887 data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps); in gpmi_nfc_compute_timings()
888 data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps); in gpmi_nfc_compute_timings()
890 busy_timeout_cycles = TO_CYCLES(busy_timeout_ps, period_ps); in gpmi_nfc_compute_timings()