1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17
18 #include <sound/asoundef.h>
19 #include <sound/core.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm_params.h>
22
23 #include "stm32_sai.h"
24
25 #define SAI_FREE_PROTOCOL 0x0
26 #define SAI_SPDIF_PROTOCOL 0x1
27
28 #define SAI_SLOT_SIZE_AUTO 0x0
29 #define SAI_SLOT_SIZE_16 0x1
30 #define SAI_SLOT_SIZE_32 0x2
31
32 #define SAI_DATASIZE_8 0x2
33 #define SAI_DATASIZE_10 0x3
34 #define SAI_DATASIZE_16 0x4
35 #define SAI_DATASIZE_20 0x5
36 #define SAI_DATASIZE_24 0x6
37 #define SAI_DATASIZE_32 0x7
38
39 #define STM_SAI_DAI_NAME_SIZE 15
40
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
43
44 #define STM_SAI_A_ID 0x0
45 #define STM_SAI_B_ID 0x1
46
47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
48
49 #define SAI_SYNC_NONE 0x0
50 #define SAI_SYNC_INTERNAL 0x1
51 #define SAI_SYNC_EXTERNAL 0x2
52
53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4((x)->pdata))
57
58 #define SAI_IEC60958_BLOCK_FRAMES 192
59 #define SAI_IEC60958_STATUS_BYTES 24
60
61 #define SAI_MCLK_NAME_LEN 32
62 #define SAI_RATE_11K 11025
63 #define SAI_MAX_SAMPLE_RATE_8K 192000
64 #define SAI_MAX_SAMPLE_RATE_11K 176400
65 #define SAI_CK_RATE_TOLERANCE 1000 /* ppm */
66
67 /**
68 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
69 * @pdev: device data pointer
70 * @regmap: SAI register map pointer
71 * @regmap_config: SAI sub block register map configuration pointer
72 * @dma_params: dma configuration data for rx or tx channel
73 * @cpu_dai_drv: DAI driver data pointer
74 * @cpu_dai: DAI runtime data pointer
75 * @substream: PCM substream data pointer
76 * @pdata: SAI block parent data pointer
77 * @np_sync_provider: synchronization provider node
78 * @sai_ck: kernel clock feeding the SAI clock generator
79 * @sai_mclk: master clock from SAI mclk provider
80 * @phys_addr: SAI registers physical base address
81 * @mclk_rate: SAI block master clock frequency (Hz). set at init
82 * @id: SAI sub block id corresponding to sub-block A or B
83 * @dir: SAI block direction (playback or capture). set at init
84 * @master: SAI block mode flag. (true=master, false=slave) set at init
85 * @spdif: SAI S/PDIF iec60958 mode flag. set at init
86 * @sai_ck_used: flag set while exclusivity on SAI kernel clock is active
87 * @fmt: SAI block format. relevant only for custom protocols. set at init
88 * @sync: SAI block synchronization mode. (none, internal or external)
89 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
90 * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
91 * @fs_length: frame synchronization length. depends on protocol settings
92 * @slots: rx or tx slot number
93 * @slot_width: rx or tx slot width in bits
94 * @slot_mask: rx or tx active slots mask. set at init or at runtime
95 * @data_size: PCM data width. corresponds to PCM substream width.
96 * @spdif_frm_cnt: S/PDIF playback frame counter
97 * @iec958: iec958 data
98 * @ctrl_lock: control lock
99 * @irq_lock: prevent race condition with IRQ
100 * @set_sai_ck_rate: set SAI kernel clock rate
101 * @put_sai_ck_rate: put SAI kernel clock rate
102 */
103 struct stm32_sai_sub_data {
104 struct platform_device *pdev;
105 struct regmap *regmap;
106 const struct regmap_config *regmap_config;
107 struct snd_dmaengine_dai_dma_data dma_params;
108 struct snd_soc_dai_driver cpu_dai_drv;
109 struct snd_soc_dai *cpu_dai;
110 struct snd_pcm_substream *substream;
111 struct stm32_sai_data *pdata;
112 struct device_node *np_sync_provider;
113 struct clk *sai_ck;
114 struct clk *sai_mclk;
115 dma_addr_t phys_addr;
116 unsigned int mclk_rate;
117 unsigned int id;
118 int dir;
119 bool master;
120 bool spdif;
121 bool sai_ck_used;
122 int fmt;
123 int sync;
124 int synco;
125 int synci;
126 int fs_length;
127 int slots;
128 int slot_width;
129 int slot_mask;
130 int data_size;
131 unsigned int spdif_frm_cnt;
132 struct snd_aes_iec958 iec958;
133 struct mutex ctrl_lock; /* protect resources accessed by controls */
134 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
135 int (*set_sai_ck_rate)(struct stm32_sai_sub_data *sai, unsigned int rate);
136 void (*put_sai_ck_rate)(struct stm32_sai_sub_data *sai);
137 };
138
139 enum stm32_sai_fifo_th {
140 STM_SAI_FIFO_TH_EMPTY,
141 STM_SAI_FIFO_TH_QUARTER,
142 STM_SAI_FIFO_TH_HALF,
143 STM_SAI_FIFO_TH_3_QUARTER,
144 STM_SAI_FIFO_TH_FULL,
145 };
146
stm32_sai_sub_readable_reg(struct device * dev,unsigned int reg)147 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
148 {
149 switch (reg) {
150 case STM_SAI_CR1_REGX:
151 case STM_SAI_CR2_REGX:
152 case STM_SAI_FRCR_REGX:
153 case STM_SAI_SLOTR_REGX:
154 case STM_SAI_IMR_REGX:
155 case STM_SAI_SR_REGX:
156 case STM_SAI_CLRFR_REGX:
157 case STM_SAI_DR_REGX:
158 case STM_SAI_PDMCR_REGX:
159 case STM_SAI_PDMLY_REGX:
160 return true;
161 default:
162 return false;
163 }
164 }
165
stm32_sai_sub_volatile_reg(struct device * dev,unsigned int reg)166 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
167 {
168 switch (reg) {
169 case STM_SAI_DR_REGX:
170 case STM_SAI_SR_REGX:
171 return true;
172 default:
173 return false;
174 }
175 }
176
stm32_sai_sub_writeable_reg(struct device * dev,unsigned int reg)177 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
178 {
179 switch (reg) {
180 case STM_SAI_CR1_REGX:
181 case STM_SAI_CR2_REGX:
182 case STM_SAI_FRCR_REGX:
183 case STM_SAI_SLOTR_REGX:
184 case STM_SAI_IMR_REGX:
185 case STM_SAI_CLRFR_REGX:
186 case STM_SAI_DR_REGX:
187 case STM_SAI_PDMCR_REGX:
188 case STM_SAI_PDMLY_REGX:
189 return true;
190 default:
191 return false;
192 }
193 }
194
stm32_sai_sub_reg_up(struct stm32_sai_sub_data * sai,unsigned int reg,unsigned int mask,unsigned int val)195 static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai,
196 unsigned int reg, unsigned int mask,
197 unsigned int val)
198 {
199 int ret;
200
201 ret = clk_enable(sai->pdata->pclk);
202 if (ret < 0)
203 return ret;
204
205 ret = regmap_update_bits(sai->regmap, reg, mask, val);
206
207 clk_disable(sai->pdata->pclk);
208
209 return ret;
210 }
211
stm32_sai_sub_reg_wr(struct stm32_sai_sub_data * sai,unsigned int reg,unsigned int mask,unsigned int val)212 static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai,
213 unsigned int reg, unsigned int mask,
214 unsigned int val)
215 {
216 int ret;
217
218 ret = clk_enable(sai->pdata->pclk);
219 if (ret < 0)
220 return ret;
221
222 ret = regmap_write_bits(sai->regmap, reg, mask, val);
223
224 clk_disable(sai->pdata->pclk);
225
226 return ret;
227 }
228
stm32_sai_sub_reg_rd(struct stm32_sai_sub_data * sai,unsigned int reg,unsigned int * val)229 static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai,
230 unsigned int reg, unsigned int *val)
231 {
232 int ret;
233
234 ret = clk_enable(sai->pdata->pclk);
235 if (ret < 0)
236 return ret;
237
238 ret = regmap_read(sai->regmap, reg, val);
239
240 clk_disable(sai->pdata->pclk);
241
242 return ret;
243 }
244
245 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
246 .reg_bits = 32,
247 .reg_stride = 4,
248 .val_bits = 32,
249 .max_register = STM_SAI_DR_REGX,
250 .readable_reg = stm32_sai_sub_readable_reg,
251 .volatile_reg = stm32_sai_sub_volatile_reg,
252 .writeable_reg = stm32_sai_sub_writeable_reg,
253 .fast_io = true,
254 .cache_type = REGCACHE_FLAT,
255 };
256
257 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
258 .reg_bits = 32,
259 .reg_stride = 4,
260 .val_bits = 32,
261 .max_register = STM_SAI_PDMLY_REGX,
262 .readable_reg = stm32_sai_sub_readable_reg,
263 .volatile_reg = stm32_sai_sub_volatile_reg,
264 .writeable_reg = stm32_sai_sub_writeable_reg,
265 .fast_io = true,
266 .cache_type = REGCACHE_FLAT,
267 };
268
snd_pcm_iec958_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)269 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
270 struct snd_ctl_elem_info *uinfo)
271 {
272 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
273 uinfo->count = 1;
274
275 return 0;
276 }
277
snd_pcm_iec958_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)278 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
279 struct snd_ctl_elem_value *uctl)
280 {
281 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
282
283 mutex_lock(&sai->ctrl_lock);
284 memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
285 mutex_unlock(&sai->ctrl_lock);
286
287 return 0;
288 }
289
snd_pcm_iec958_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)290 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
291 struct snd_ctl_elem_value *uctl)
292 {
293 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
294
295 mutex_lock(&sai->ctrl_lock);
296 memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
297 mutex_unlock(&sai->ctrl_lock);
298
299 return 0;
300 }
301
302 static const struct snd_kcontrol_new iec958_ctls = {
303 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
304 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
305 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
306 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
307 .info = snd_pcm_iec958_info,
308 .get = snd_pcm_iec958_get,
309 .put = snd_pcm_iec958_put,
310 };
311
312 struct stm32_sai_mclk_data {
313 struct clk_hw hw;
314 unsigned long freq;
315 struct stm32_sai_sub_data *sai_data;
316 };
317
318 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
319 #define STM32_SAI_MAX_CLKS 1
320
stm32_sai_get_clk_div(struct stm32_sai_sub_data * sai,unsigned long input_rate,unsigned long output_rate)321 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
322 unsigned long input_rate,
323 unsigned long output_rate)
324 {
325 int version = sai->pdata->conf.version;
326 int div;
327
328 div = DIV_ROUND_CLOSEST(input_rate, output_rate);
329 if (div > SAI_XCR1_MCKDIV_MAX(version) || div <= 0) {
330 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
331 return -EINVAL;
332 }
333 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
334
335 if (input_rate % div)
336 dev_dbg(&sai->pdev->dev,
337 "Rate not accurate. requested (%ld), actual (%ld)\n",
338 output_rate, input_rate / div);
339
340 return div;
341 }
342
stm32_sai_set_clk_div(struct stm32_sai_sub_data * sai,unsigned int div)343 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
344 unsigned int div)
345 {
346 int version = sai->pdata->conf.version;
347 int ret, cr1, mask;
348
349 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
350 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
351 return -EINVAL;
352 }
353
354 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
355 cr1 = SAI_XCR1_MCKDIV_SET(div);
356 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1);
357 if (ret < 0)
358 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
359
360 return ret;
361 }
362
stm32_sai_rate_accurate(unsigned int max_rate,unsigned int rate)363 static bool stm32_sai_rate_accurate(unsigned int max_rate, unsigned int rate)
364 {
365 u64 delta, dividend;
366 int ratio;
367
368 ratio = DIV_ROUND_CLOSEST(max_rate, rate);
369 if (!ratio)
370 return false;
371
372 dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate)));
373 delta = div_u64(dividend, max_rate);
374
375 if (delta <= SAI_CK_RATE_TOLERANCE)
376 return true;
377
378 return false;
379 }
380
stm32_sai_set_parent_clk(struct stm32_sai_sub_data * sai,unsigned int rate)381 static int stm32_sai_set_parent_clk(struct stm32_sai_sub_data *sai,
382 unsigned int rate)
383 {
384 struct platform_device *pdev = sai->pdev;
385 struct clk *parent_clk = sai->pdata->clk_x8k;
386 int ret;
387
388 if (!(rate % SAI_RATE_11K))
389 parent_clk = sai->pdata->clk_x11k;
390
391 ret = clk_set_parent(sai->sai_ck, parent_clk);
392 if (ret)
393 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s",
394 ret, ret == -EBUSY ?
395 "Active stream rates conflict\n" : "\n");
396
397 return ret;
398 }
399
stm32_sai_put_parent_rate(struct stm32_sai_sub_data * sai)400 static void stm32_sai_put_parent_rate(struct stm32_sai_sub_data *sai)
401 {
402 if (sai->sai_ck_used) {
403 sai->sai_ck_used = false;
404 clk_rate_exclusive_put(sai->sai_ck);
405 }
406 }
407
stm32_sai_set_parent_rate(struct stm32_sai_sub_data * sai,unsigned int rate)408 static int stm32_sai_set_parent_rate(struct stm32_sai_sub_data *sai,
409 unsigned int rate)
410 {
411 struct platform_device *pdev = sai->pdev;
412 unsigned int sai_ck_rate, sai_ck_max_rate, sai_ck_min_rate, sai_curr_rate, sai_new_rate;
413 int div, ret;
414
415 /*
416 * Set minimum and maximum expected kernel clock frequency
417 * - mclk on or spdif:
418 * f_sai_ck = MCKDIV * mclk-fs * fs
419 * Here typical 256 ratio is assumed for mclk-fs
420 * - mclk off:
421 * f_sai_ck = MCKDIV * FRL * fs
422 * Where FRL=[8..256], MCKDIV=[1..n] (n depends on SAI version)
423 * Set constraint MCKDIV * FRL <= 256, to ensure MCKDIV is in available range
424 * f_sai_ck = sai_ck_max_rate * pow_of_two(FRL) / 256
425 */
426 sai_ck_min_rate = rate * 256;
427 if (!(rate % SAI_RATE_11K))
428 sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_11K * 256;
429 else
430 sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_8K * 256;
431
432 if (!sai->sai_mclk && !STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
433 sai_ck_min_rate = rate * sai->fs_length;
434 sai_ck_max_rate /= DIV_ROUND_CLOSEST(256, roundup_pow_of_two(sai->fs_length));
435 }
436
437 /*
438 * Request exclusivity, as the clock is shared by SAI sub-blocks and by
439 * some SAI instances. This allows to ensure that the rate cannot be
440 * changed while one or more SAIs are using the clock.
441 */
442 clk_rate_exclusive_get(sai->sai_ck);
443 sai->sai_ck_used = true;
444
445 /*
446 * Check current kernel clock rate. If it gives the expected accuracy
447 * return immediately.
448 */
449 sai_curr_rate = clk_get_rate(sai->sai_ck);
450 dev_dbg(&pdev->dev, "kernel clock rate: min [%u], max [%u], current [%u]",
451 sai_ck_min_rate, sai_ck_max_rate, sai_curr_rate);
452 if (stm32_sai_rate_accurate(sai_ck_max_rate, sai_curr_rate) &&
453 sai_curr_rate >= sai_ck_min_rate)
454 return 0;
455
456 /*
457 * Otherwise try to set the maximum rate and check the new actual rate.
458 * If the new rate does not give the expected accuracy, try to set
459 * lower rates for the kernel clock.
460 */
461 sai_ck_rate = sai_ck_max_rate;
462 div = 1;
463 do {
464 /* Check new rate accuracy. Return if ok */
465 sai_new_rate = clk_round_rate(sai->sai_ck, sai_ck_rate);
466 if (stm32_sai_rate_accurate(sai_ck_rate, sai_new_rate)) {
467 ret = clk_set_rate(sai->sai_ck, sai_ck_rate);
468 if (ret) {
469 dev_err(&pdev->dev, "Error %d setting sai_ck rate. %s",
470 ret, ret == -EBUSY ?
471 "Active stream rates may be in conflict\n" : "\n");
472 goto err;
473 }
474
475 return 0;
476 }
477
478 /* Try a lower frequency */
479 div++;
480 sai_ck_rate = sai_ck_max_rate / div;
481 } while (sai_ck_rate >= sai_ck_min_rate);
482
483 /* No accurate rate found */
484 dev_err(&pdev->dev, "Failed to find an accurate rate");
485
486 err:
487 stm32_sai_put_parent_rate(sai);
488
489 return -EINVAL;
490 }
491
stm32_sai_mclk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)492 static int stm32_sai_mclk_determine_rate(struct clk_hw *hw,
493 struct clk_rate_request *req)
494 {
495 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
496 struct stm32_sai_sub_data *sai = mclk->sai_data;
497 int div;
498
499 div = stm32_sai_get_clk_div(sai, req->best_parent_rate, req->rate);
500 if (div <= 0)
501 return -EINVAL;
502
503 mclk->freq = req->best_parent_rate / div;
504
505 req->rate = mclk->freq;
506
507 return 0;
508 }
509
stm32_sai_mclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)510 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
511 unsigned long parent_rate)
512 {
513 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
514
515 return mclk->freq;
516 }
517
stm32_sai_mclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)518 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
519 unsigned long parent_rate)
520 {
521 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
522 struct stm32_sai_sub_data *sai = mclk->sai_data;
523 int div, ret;
524
525 div = stm32_sai_get_clk_div(sai, parent_rate, rate);
526 if (div < 0)
527 return div;
528
529 ret = stm32_sai_set_clk_div(sai, div);
530 if (ret)
531 return ret;
532
533 mclk->freq = rate;
534
535 return 0;
536 }
537
stm32_sai_mclk_enable(struct clk_hw * hw)538 static int stm32_sai_mclk_enable(struct clk_hw *hw)
539 {
540 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
541 struct stm32_sai_sub_data *sai = mclk->sai_data;
542
543 dev_dbg(&sai->pdev->dev, "Enable master clock\n");
544
545 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
546 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
547 }
548
stm32_sai_mclk_disable(struct clk_hw * hw)549 static void stm32_sai_mclk_disable(struct clk_hw *hw)
550 {
551 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
552 struct stm32_sai_sub_data *sai = mclk->sai_data;
553
554 dev_dbg(&sai->pdev->dev, "Disable master clock\n");
555
556 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
557 }
558
559 static const struct clk_ops mclk_ops = {
560 .enable = stm32_sai_mclk_enable,
561 .disable = stm32_sai_mclk_disable,
562 .recalc_rate = stm32_sai_mclk_recalc_rate,
563 .determine_rate = stm32_sai_mclk_determine_rate,
564 .set_rate = stm32_sai_mclk_set_rate,
565 };
566
stm32_sai_add_mclk_provider(struct stm32_sai_sub_data * sai)567 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
568 {
569 struct clk_hw *hw;
570 struct stm32_sai_mclk_data *mclk;
571 struct device *dev = &sai->pdev->dev;
572 const char *pname = __clk_get_name(sai->sai_ck);
573 char *mclk_name, *p, *s = (char *)pname;
574 int ret, i = 0;
575
576 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
577 if (!mclk)
578 return -ENOMEM;
579
580 mclk_name = devm_kcalloc(dev, sizeof(char),
581 SAI_MCLK_NAME_LEN, GFP_KERNEL);
582 if (!mclk_name)
583 return -ENOMEM;
584
585 /*
586 * Forge mclk clock name from parent clock name and suffix.
587 * String after "_" char is stripped in parent name.
588 */
589 p = mclk_name;
590 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) {
591 *p++ = *s++;
592 i++;
593 }
594 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk");
595
596 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
597 mclk->sai_data = sai;
598 hw = &mclk->hw;
599
600 dev_dbg(dev, "Register master clock %s\n", mclk_name);
601 ret = devm_clk_hw_register(&sai->pdev->dev, hw);
602 if (ret) {
603 dev_err(dev, "mclk register returned %d\n", ret);
604 return ret;
605 }
606 sai->sai_mclk = hw->clk;
607
608 /* register mclk provider */
609 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
610 }
611
stm32_sai_isr(int irq,void * devid)612 static irqreturn_t stm32_sai_isr(int irq, void *devid)
613 {
614 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
615 struct platform_device *pdev = sai->pdev;
616 unsigned int sr, imr, flags;
617 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
618
619 stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr);
620 stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr);
621
622 flags = sr & imr;
623 if (!flags)
624 return IRQ_NONE;
625
626 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
627 SAI_XCLRFR_MASK);
628
629 if (!sai->substream) {
630 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
631 return IRQ_NONE;
632 }
633
634 if (flags & SAI_XIMR_OVRUDRIE) {
635 dev_err(&pdev->dev, "IRQ %s\n",
636 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
637 status = SNDRV_PCM_STATE_XRUN;
638 }
639
640 if (flags & SAI_XIMR_MUTEDETIE)
641 dev_dbg(&pdev->dev, "IRQ mute detected\n");
642
643 if (flags & SAI_XIMR_WCKCFGIE) {
644 dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
645 status = SNDRV_PCM_STATE_DISCONNECTED;
646 }
647
648 if (flags & SAI_XIMR_CNRDYIE)
649 dev_err(&pdev->dev, "IRQ Codec not ready\n");
650
651 if (flags & SAI_XIMR_AFSDETIE) {
652 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
653 status = SNDRV_PCM_STATE_XRUN;
654 }
655
656 if (flags & SAI_XIMR_LFSDETIE) {
657 dev_err(&pdev->dev, "IRQ Late frame synchro\n");
658 status = SNDRV_PCM_STATE_XRUN;
659 }
660
661 spin_lock(&sai->irq_lock);
662 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
663 snd_pcm_stop_xrun(sai->substream);
664 spin_unlock(&sai->irq_lock);
665
666 return IRQ_HANDLED;
667 }
668
stm32_sai_set_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)669 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
670 int clk_id, unsigned int freq, int dir)
671 {
672 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
673 int ret;
674
675 /*
676 * The mclk rate is determined at runtime from the audio stream rate.
677 * Skip calls to the set_sysclk callback that are not relevant during the
678 * initialization phase.
679 */
680 if (!snd_soc_card_is_instantiated(cpu_dai->component->card))
681 return 0;
682
683 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) {
684 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
685 SAI_XCR1_NODIV,
686 freq ? 0 : SAI_XCR1_NODIV);
687 if (ret < 0)
688 return ret;
689
690 /* Assume shutdown if requested frequency is 0Hz */
691 if (!freq) {
692 /* Release mclk rate only if rate was actually set */
693 if (sai->mclk_rate) {
694 clk_rate_exclusive_put(sai->sai_mclk);
695 sai->mclk_rate = 0;
696 }
697
698 if (sai->put_sai_ck_rate)
699 sai->put_sai_ck_rate(sai);
700
701 return 0;
702 }
703
704 /* If master clock is used, configure SAI kernel clock now */
705 ret = sai->set_sai_ck_rate(sai, freq);
706 if (ret)
707 return ret;
708
709 ret = clk_set_rate_exclusive(sai->sai_mclk, freq);
710 if (ret) {
711 dev_err(cpu_dai->dev,
712 ret == -EBUSY ?
713 "Active streams have incompatible rates" :
714 "Could not set mclk rate\n");
715 return ret;
716 }
717
718 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
719 sai->mclk_rate = freq;
720 }
721
722 return 0;
723 }
724
stm32_sai_set_dai_tdm_slot(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)725 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
726 u32 rx_mask, int slots, int slot_width)
727 {
728 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
729 int slotr, slotr_mask, slot_size;
730
731 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
732 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
733 return 0;
734 }
735
736 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
737 tx_mask, rx_mask, slots, slot_width);
738
739 switch (slot_width) {
740 case 16:
741 slot_size = SAI_SLOT_SIZE_16;
742 break;
743 case 32:
744 slot_size = SAI_SLOT_SIZE_32;
745 break;
746 default:
747 slot_size = SAI_SLOT_SIZE_AUTO;
748 break;
749 }
750
751 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
752 SAI_XSLOTR_NBSLOT_SET(slots - 1);
753 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
754
755 /* tx/rx mask set in machine init, if slot number defined in DT */
756 if (STM_SAI_IS_PLAYBACK(sai)) {
757 sai->slot_mask = tx_mask;
758 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
759 }
760
761 if (STM_SAI_IS_CAPTURE(sai)) {
762 sai->slot_mask = rx_mask;
763 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
764 }
765
766 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
767
768 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
769
770 sai->slot_width = slot_width;
771 sai->slots = slots;
772
773 return 0;
774 }
775
stm32_sai_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)776 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
777 {
778 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
779 int cr1, frcr = 0;
780 int cr1_mask, frcr_mask = 0;
781 int ret;
782
783 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
784
785 /* Do not generate master by default */
786 cr1 = SAI_XCR1_NODIV;
787 cr1_mask = SAI_XCR1_NODIV;
788
789 cr1_mask |= SAI_XCR1_PRTCFG_MASK;
790 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
791 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
792 goto conf_update;
793 }
794
795 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
796
797 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
798 /* SCK active high for all protocols */
799 case SND_SOC_DAIFMT_I2S:
800 cr1 |= SAI_XCR1_CKSTR;
801 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
802 break;
803 /* Left justified */
804 case SND_SOC_DAIFMT_MSB:
805 cr1 |= SAI_XCR1_CKSTR;
806 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
807 break;
808 /* Right justified */
809 case SND_SOC_DAIFMT_LSB:
810 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
811 break;
812 case SND_SOC_DAIFMT_DSP_A:
813 cr1 |= SAI_XCR1_CKSTR;
814 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
815 break;
816 case SND_SOC_DAIFMT_DSP_B:
817 cr1 |= SAI_XCR1_CKSTR;
818 frcr |= SAI_XFRCR_FSPOL;
819 break;
820 default:
821 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
822 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
823 return -EINVAL;
824 }
825
826 cr1_mask |= SAI_XCR1_CKSTR;
827 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
828 SAI_XFRCR_FSDEF;
829
830 /* DAI clock strobing. Invert setting previously set */
831 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
832 case SND_SOC_DAIFMT_NB_NF:
833 break;
834 case SND_SOC_DAIFMT_IB_NF:
835 cr1 ^= SAI_XCR1_CKSTR;
836 break;
837 case SND_SOC_DAIFMT_NB_IF:
838 frcr ^= SAI_XFRCR_FSPOL;
839 break;
840 case SND_SOC_DAIFMT_IB_IF:
841 /* Invert fs & sck */
842 cr1 ^= SAI_XCR1_CKSTR;
843 frcr ^= SAI_XFRCR_FSPOL;
844 break;
845 default:
846 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
847 fmt & SND_SOC_DAIFMT_INV_MASK);
848 return -EINVAL;
849 }
850 cr1_mask |= SAI_XCR1_CKSTR;
851 frcr_mask |= SAI_XFRCR_FSPOL;
852
853 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
854
855 /* DAI clock master masks */
856 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
857 case SND_SOC_DAIFMT_BC_FC:
858 /* codec is master */
859 cr1 |= SAI_XCR1_SLAVE;
860 sai->master = false;
861 break;
862 case SND_SOC_DAIFMT_BP_FP:
863 sai->master = true;
864 break;
865 default:
866 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
867 fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
868 return -EINVAL;
869 }
870
871 /* Set slave mode if sub-block is synchronized with another SAI */
872 if (sai->sync) {
873 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
874 cr1 |= SAI_XCR1_SLAVE;
875 sai->master = false;
876 }
877
878 cr1_mask |= SAI_XCR1_SLAVE;
879
880 conf_update:
881 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
882 if (ret < 0) {
883 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
884 return ret;
885 }
886
887 sai->fmt = fmt;
888
889 return 0;
890 }
891
stm32_sai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)892 static int stm32_sai_startup(struct snd_pcm_substream *substream,
893 struct snd_soc_dai *cpu_dai)
894 {
895 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
896 int imr, cr2, ret;
897 unsigned long flags;
898
899 spin_lock_irqsave(&sai->irq_lock, flags);
900 sai->substream = substream;
901 spin_unlock_irqrestore(&sai->irq_lock, flags);
902
903 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
904 snd_pcm_hw_constraint_mask64(substream->runtime,
905 SNDRV_PCM_HW_PARAM_FORMAT,
906 SNDRV_PCM_FMTBIT_S32_LE);
907 snd_pcm_hw_constraint_single(substream->runtime,
908 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
909 }
910
911 ret = clk_prepare_enable(sai->sai_ck);
912 if (ret < 0) {
913 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
914 return ret;
915 }
916
917 /* Enable ITs */
918 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX,
919 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
920
921 imr = SAI_XIMR_OVRUDRIE;
922 if (STM_SAI_IS_CAPTURE(sai)) {
923 stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2);
924 if (cr2 & SAI_XCR2_MUTECNT_MASK)
925 imr |= SAI_XIMR_MUTEDETIE;
926 }
927
928 if (sai->master)
929 imr |= SAI_XIMR_WCKCFGIE;
930 else
931 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
932
933 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
934 SAI_XIMR_MASK, imr);
935
936 return 0;
937 }
938
stm32_sai_set_config(struct snd_soc_dai * cpu_dai,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)939 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
940 struct snd_pcm_substream *substream,
941 struct snd_pcm_hw_params *params)
942 {
943 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
944 int cr1, cr1_mask, ret;
945
946 /*
947 * DMA bursts increment is set to 4 words.
948 * SAI fifo threshold is set to half fifo, to keep enough space
949 * for DMA incoming bursts.
950 */
951 stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX,
952 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
953 SAI_XCR2_FFLUSH |
954 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
955
956 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
957 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
958 sai->spdif_frm_cnt = 0;
959 return 0;
960 }
961
962 /* Mode, data format and channel config */
963 cr1_mask = SAI_XCR1_DS_MASK;
964 switch (params_format(params)) {
965 case SNDRV_PCM_FORMAT_S8:
966 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
967 break;
968 case SNDRV_PCM_FORMAT_S16_LE:
969 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
970 break;
971 case SNDRV_PCM_FORMAT_S32_LE:
972 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
973 break;
974 default:
975 dev_err(cpu_dai->dev, "Data format not supported\n");
976 return -EINVAL;
977 }
978
979 cr1_mask |= SAI_XCR1_MONO;
980 if ((sai->slots == 2) && (params_channels(params) == 1))
981 cr1 |= SAI_XCR1_MONO;
982
983 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
984 if (ret < 0) {
985 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
986 return ret;
987 }
988
989 return 0;
990 }
991
stm32_sai_set_slots(struct snd_soc_dai * cpu_dai)992 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
993 {
994 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
995 int slotr, slot_sz;
996
997 stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr);
998
999 /*
1000 * If SLOTSZ is set to auto in SLOTR, align slot width on data size
1001 * By default slot width = data size, if not forced from DT
1002 */
1003 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
1004 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
1005 sai->slot_width = sai->data_size;
1006
1007 if (sai->slot_width < sai->data_size) {
1008 dev_err(cpu_dai->dev,
1009 "Data size %d larger than slot width\n",
1010 sai->data_size);
1011 return -EINVAL;
1012 }
1013
1014 /* Slot number is set to 2, if not specified in DT */
1015 if (!sai->slots)
1016 sai->slots = 2;
1017
1018 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
1019 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
1020 SAI_XSLOTR_NBSLOT_MASK,
1021 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
1022
1023 /* Set default slots mask if not already set from DT */
1024 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
1025 sai->slot_mask = (1 << sai->slots) - 1;
1026 stm32_sai_sub_reg_up(sai,
1027 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
1028 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
1029 }
1030
1031 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
1032 sai->slots, sai->slot_width);
1033
1034 return 0;
1035 }
1036
stm32_sai_set_frame(struct snd_soc_dai * cpu_dai)1037 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
1038 {
1039 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1040 int fs_active, offset, format;
1041 int frcr, frcr_mask;
1042
1043 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1044 sai->fs_length = sai->slot_width * sai->slots;
1045
1046 fs_active = sai->fs_length / 2;
1047 if ((format == SND_SOC_DAIFMT_DSP_A) ||
1048 (format == SND_SOC_DAIFMT_DSP_B))
1049 fs_active = 1;
1050
1051 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
1052 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
1053 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
1054
1055 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
1056 sai->fs_length, fs_active);
1057
1058 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
1059
1060 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
1061 offset = sai->slot_width - sai->data_size;
1062
1063 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
1064 SAI_XSLOTR_FBOFF_MASK,
1065 SAI_XSLOTR_FBOFF_SET(offset));
1066 }
1067 }
1068
stm32_sai_init_iec958_status(struct stm32_sai_sub_data * sai)1069 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
1070 {
1071 unsigned char *cs = sai->iec958.status;
1072
1073 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
1074 cs[1] = IEC958_AES1_CON_GENERAL;
1075 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
1076 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
1077 }
1078
stm32_sai_set_iec958_status(struct stm32_sai_sub_data * sai,struct snd_pcm_runtime * runtime)1079 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
1080 struct snd_pcm_runtime *runtime)
1081 {
1082 if (!runtime)
1083 return;
1084
1085 /* Force the sample rate according to runtime rate */
1086 mutex_lock(&sai->ctrl_lock);
1087 switch (runtime->rate) {
1088 case 22050:
1089 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
1090 break;
1091 case 44100:
1092 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
1093 break;
1094 case 88200:
1095 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
1096 break;
1097 case 176400:
1098 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
1099 break;
1100 case 24000:
1101 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
1102 break;
1103 case 48000:
1104 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
1105 break;
1106 case 96000:
1107 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
1108 break;
1109 case 192000:
1110 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
1111 break;
1112 case 32000:
1113 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
1114 break;
1115 default:
1116 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
1117 break;
1118 }
1119 mutex_unlock(&sai->ctrl_lock);
1120 }
1121
stm32_sai_configure_clock(struct snd_soc_dai * cpu_dai,struct snd_pcm_hw_params * params)1122 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
1123 struct snd_pcm_hw_params *params)
1124 {
1125 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1126 int div = 0, cr1 = 0;
1127 int sai_clk_rate, mclk_ratio, den;
1128 unsigned int rate = params_rate(params);
1129 int ret;
1130
1131 if (!sai->sai_mclk) {
1132 ret = sai->set_sai_ck_rate(sai, rate);
1133 if (ret)
1134 return ret;
1135 }
1136 sai_clk_rate = clk_get_rate(sai->sai_ck);
1137
1138 if (STM_SAI_IS_F4(sai->pdata)) {
1139 /* mclk on (NODIV=0)
1140 * mclk_rate = 256 * fs
1141 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
1142 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise
1143 * mclk off (NODIV=1)
1144 * MCKDIV ignored. sck = sai_ck
1145 */
1146 if (!sai->mclk_rate)
1147 return 0;
1148
1149 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
1150 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1151 2 * sai->mclk_rate);
1152 if (div < 0)
1153 return div;
1154 }
1155 } else {
1156 /*
1157 * TDM mode :
1158 * mclk on
1159 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
1160 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
1161 * mclk off
1162 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
1163 * Note: NOMCK/NODIV correspond to same bit.
1164 */
1165 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1166 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1167 rate * 128);
1168 if (div < 0)
1169 return div;
1170 } else {
1171 if (sai->mclk_rate) {
1172 mclk_ratio = sai->mclk_rate / rate;
1173 if (mclk_ratio == 512) {
1174 cr1 = SAI_XCR1_OSR;
1175 } else if (mclk_ratio != 256) {
1176 dev_err(cpu_dai->dev,
1177 "Wrong mclk ratio %d\n",
1178 mclk_ratio);
1179 return -EINVAL;
1180 }
1181
1182 stm32_sai_sub_reg_up(sai,
1183 STM_SAI_CR1_REGX,
1184 SAI_XCR1_OSR, cr1);
1185
1186 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1187 sai->mclk_rate);
1188 if (div < 0)
1189 return div;
1190 } else {
1191 /* mclk-fs not set, master clock not active */
1192 den = sai->fs_length * params_rate(params);
1193 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1194 den);
1195 if (div < 0)
1196 return div;
1197 }
1198 }
1199 }
1200
1201 return stm32_sai_set_clk_div(sai, div);
1202 }
1203
stm32_sai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)1204 static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
1205 struct snd_pcm_hw_params *params,
1206 struct snd_soc_dai *cpu_dai)
1207 {
1208 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1209 int ret;
1210
1211 sai->data_size = params_width(params);
1212
1213 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1214 /* Rate not already set in runtime structure */
1215 substream->runtime->rate = params_rate(params);
1216 stm32_sai_set_iec958_status(sai, substream->runtime);
1217 } else {
1218 ret = stm32_sai_set_slots(cpu_dai);
1219 if (ret < 0)
1220 return ret;
1221 stm32_sai_set_frame(cpu_dai);
1222 }
1223
1224 ret = stm32_sai_set_config(cpu_dai, substream, params);
1225 if (ret)
1226 return ret;
1227
1228 if (sai->master)
1229 ret = stm32_sai_configure_clock(cpu_dai, params);
1230
1231 return ret;
1232 }
1233
stm32_sai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)1234 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
1235 struct snd_soc_dai *cpu_dai)
1236 {
1237 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1238 int ret;
1239
1240 switch (cmd) {
1241 case SNDRV_PCM_TRIGGER_START:
1242 case SNDRV_PCM_TRIGGER_RESUME:
1243 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1244 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
1245
1246 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1247 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
1248
1249 /* Enable SAI */
1250 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1251 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
1252 if (ret < 0)
1253 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1254 break;
1255 case SNDRV_PCM_TRIGGER_SUSPEND:
1256 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1257 case SNDRV_PCM_TRIGGER_STOP:
1258 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
1259
1260 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
1261 SAI_XIMR_MASK, 0);
1262
1263 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1264 SAI_XCR1_SAIEN,
1265 (unsigned int)~SAI_XCR1_SAIEN);
1266
1267 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1268 SAI_XCR1_DMAEN,
1269 (unsigned int)~SAI_XCR1_DMAEN);
1270 if (ret < 0)
1271 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1272
1273 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1274 sai->spdif_frm_cnt = 0;
1275 break;
1276 default:
1277 return -EINVAL;
1278 }
1279
1280 return ret;
1281 }
1282
stm32_sai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1283 static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
1284 struct snd_soc_dai *cpu_dai)
1285 {
1286 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1287 unsigned long flags;
1288
1289 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
1290
1291 clk_disable_unprepare(sai->sai_ck);
1292
1293 /*
1294 * Release kernel clock if following conditions are fulfilled
1295 * - Master clock is not used. Kernel clock won't be released trough sysclk
1296 * - Put handler is defined. Involve that clock is managed exclusively
1297 */
1298 if (!sai->sai_mclk && sai->put_sai_ck_rate)
1299 sai->put_sai_ck_rate(sai);
1300
1301 spin_lock_irqsave(&sai->irq_lock, flags);
1302 sai->substream = NULL;
1303 spin_unlock_irqrestore(&sai->irq_lock, flags);
1304 }
1305
stm32_sai_pcm_new(struct snd_soc_pcm_runtime * rtd,struct snd_soc_dai * cpu_dai)1306 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
1307 struct snd_soc_dai *cpu_dai)
1308 {
1309 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1310 struct snd_kcontrol_new knew = iec958_ctls;
1311
1312 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1313 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
1314 knew.device = rtd->pcm->device;
1315 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai));
1316 }
1317
1318 return 0;
1319 }
1320
stm32_sai_dai_probe(struct snd_soc_dai * cpu_dai)1321 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
1322 {
1323 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1324 int cr1 = 0, cr1_mask, ret;
1325
1326 sai->cpu_dai = cpu_dai;
1327
1328 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
1329 /*
1330 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
1331 * as it allows bytes, half-word and words transfers. (See DMA fifos
1332 * constraints).
1333 */
1334 sai->dma_params.maxburst = 4;
1335 if (sai->pdata->conf.fifo_size < 8 || sai->pdata->conf.no_dma_burst)
1336 sai->dma_params.maxburst = 1;
1337 /* Buswidth will be set by framework at runtime */
1338 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1339
1340 if (STM_SAI_IS_PLAYBACK(sai))
1341 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
1342 else
1343 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
1344
1345 /* Next settings are not relevant for spdif mode */
1346 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1347 return 0;
1348
1349 cr1_mask = SAI_XCR1_RX_TX;
1350 if (STM_SAI_IS_CAPTURE(sai))
1351 cr1 |= SAI_XCR1_RX_TX;
1352
1353 /* Configure synchronization */
1354 if (sai->sync == SAI_SYNC_EXTERNAL) {
1355 /* Configure synchro client and provider */
1356 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
1357 sai->synco, sai->synci);
1358 if (ret)
1359 return ret;
1360 }
1361
1362 cr1_mask |= SAI_XCR1_SYNCEN_MASK;
1363 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
1364
1365 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
1366 }
1367
1368 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
1369 .probe = stm32_sai_dai_probe,
1370 .set_sysclk = stm32_sai_set_sysclk,
1371 .set_fmt = stm32_sai_set_dai_fmt,
1372 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
1373 .startup = stm32_sai_startup,
1374 .hw_params = stm32_sai_hw_params,
1375 .trigger = stm32_sai_trigger,
1376 .shutdown = stm32_sai_shutdown,
1377 .pcm_new = stm32_sai_pcm_new,
1378 };
1379
1380 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops2 = {
1381 .probe = stm32_sai_dai_probe,
1382 .set_sysclk = stm32_sai_set_sysclk,
1383 .set_fmt = stm32_sai_set_dai_fmt,
1384 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
1385 .startup = stm32_sai_startup,
1386 .hw_params = stm32_sai_hw_params,
1387 .trigger = stm32_sai_trigger,
1388 .shutdown = stm32_sai_shutdown,
1389 };
1390
stm32_sai_pcm_process_spdif(struct snd_pcm_substream * substream,int channel,unsigned long hwoff,unsigned long bytes)1391 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
1392 int channel, unsigned long hwoff,
1393 unsigned long bytes)
1394 {
1395 struct snd_pcm_runtime *runtime = substream->runtime;
1396 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1397 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
1398 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1399 int *ptr = (int *)(runtime->dma_area + hwoff +
1400 channel * (runtime->dma_bytes / runtime->channels));
1401 ssize_t cnt = bytes_to_samples(runtime, bytes);
1402 unsigned int frm_cnt = sai->spdif_frm_cnt;
1403 unsigned int byte;
1404 unsigned int mask;
1405
1406 do {
1407 *ptr = ((*ptr >> 8) & 0x00ffffff);
1408
1409 /* Set channel status bit */
1410 byte = frm_cnt >> 3;
1411 mask = 1 << (frm_cnt - (byte << 3));
1412 if (sai->iec958.status[byte] & mask)
1413 *ptr |= 0x04000000;
1414 ptr++;
1415
1416 if (!(cnt % 2))
1417 frm_cnt++;
1418
1419 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
1420 frm_cnt = 0;
1421 } while (--cnt);
1422 sai->spdif_frm_cnt = frm_cnt;
1423
1424 return 0;
1425 }
1426
1427 /* No support of mmap in S/PDIF mode */
1428 static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = {
1429 .info = SNDRV_PCM_INFO_INTERLEAVED,
1430 .buffer_bytes_max = 8 * PAGE_SIZE,
1431 .period_bytes_min = 1024,
1432 .period_bytes_max = PAGE_SIZE,
1433 .periods_min = 2,
1434 .periods_max = 8,
1435 };
1436
1437 static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
1438 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1439 .buffer_bytes_max = 8 * PAGE_SIZE,
1440 .period_bytes_min = 1024, /* 5ms at 48kHz */
1441 .period_bytes_max = PAGE_SIZE,
1442 .periods_min = 2,
1443 .periods_max = 8,
1444 };
1445
1446 static struct snd_soc_dai_driver stm32_sai_playback_dai = {
1447 .id = 1, /* avoid call to fmt_single_name() */
1448 .playback = {
1449 .channels_min = 1,
1450 .channels_max = 16,
1451 .rate_min = 8000,
1452 .rate_max = 192000,
1453 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1454 /* DMA does not support 24 bits transfers */
1455 .formats =
1456 SNDRV_PCM_FMTBIT_S8 |
1457 SNDRV_PCM_FMTBIT_S16_LE |
1458 SNDRV_PCM_FMTBIT_S32_LE,
1459 },
1460 .ops = &stm32_sai_pcm_dai_ops,
1461 };
1462
1463 static struct snd_soc_dai_driver stm32_sai_capture_dai = {
1464 .id = 1, /* avoid call to fmt_single_name() */
1465 .capture = {
1466 .channels_min = 1,
1467 .channels_max = 16,
1468 .rate_min = 8000,
1469 .rate_max = 192000,
1470 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1471 /* DMA does not support 24 bits transfers */
1472 .formats =
1473 SNDRV_PCM_FMTBIT_S8 |
1474 SNDRV_PCM_FMTBIT_S16_LE |
1475 SNDRV_PCM_FMTBIT_S32_LE,
1476 },
1477 .ops = &stm32_sai_pcm_dai_ops2,
1478 };
1479
1480 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
1481 .pcm_hardware = &stm32_sai_pcm_hw,
1482 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1483 };
1484
1485 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
1486 .pcm_hardware = &stm32_sai_pcm_hw_spdif,
1487 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1488 .process = stm32_sai_pcm_process_spdif,
1489 };
1490
1491 static const struct snd_soc_component_driver stm32_component = {
1492 .name = "stm32-sai",
1493 .legacy_dai_naming = 1,
1494 };
1495
1496 static const struct of_device_id stm32_sai_sub_ids[] = {
1497 { .compatible = "st,stm32-sai-sub-a",
1498 .data = (void *)STM_SAI_A_ID},
1499 { .compatible = "st,stm32-sai-sub-b",
1500 .data = (void *)STM_SAI_B_ID},
1501 {}
1502 };
1503 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
1504
stm32_sai_sub_parse_of(struct platform_device * pdev,struct stm32_sai_sub_data * sai)1505 static int stm32_sai_sub_parse_of(struct platform_device *pdev,
1506 struct stm32_sai_sub_data *sai)
1507 {
1508 struct device_node *np = pdev->dev.of_node;
1509 struct resource *res;
1510 void __iomem *base;
1511 struct of_phandle_args args;
1512 int ret;
1513
1514 if (!np)
1515 return -ENODEV;
1516
1517 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1518 if (IS_ERR(base))
1519 return PTR_ERR(base);
1520
1521 sai->phys_addr = res->start;
1522
1523 sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
1524 /* Note: PDM registers not available for sub-block B */
1525 if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai))
1526 sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
1527
1528 /*
1529 * Do not manage peripheral clock through regmap framework as this
1530 * can lead to circular locking issue with sai master clock provider.
1531 * Manage peripheral clock directly in driver instead.
1532 */
1533 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1534 sai->regmap_config);
1535 if (IS_ERR(sai->regmap))
1536 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap),
1537 "Regmap init error\n");
1538
1539 /* Get direction property */
1540 if (of_property_match_string(np, "dma-names", "tx") >= 0) {
1541 sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
1542 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
1543 sai->dir = SNDRV_PCM_STREAM_CAPTURE;
1544 } else {
1545 dev_err(&pdev->dev, "Unsupported direction\n");
1546 return -EINVAL;
1547 }
1548
1549 /* Get spdif iec60958 property */
1550 sai->spdif = false;
1551 if (of_property_present(np, "st,iec60958")) {
1552 if (!STM_SAI_HAS_SPDIF(sai) ||
1553 sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
1554 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
1555 return -EINVAL;
1556 }
1557 stm32_sai_init_iec958_status(sai);
1558 sai->spdif = true;
1559 sai->master = true;
1560 }
1561
1562 /* Get synchronization property */
1563 args.np = NULL;
1564 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
1565 if (ret < 0 && ret != -ENOENT) {
1566 dev_err(&pdev->dev, "Failed to get st,sync property\n");
1567 return ret;
1568 }
1569
1570 sai->sync = SAI_SYNC_NONE;
1571 if (args.np) {
1572 if (args.np == np) {
1573 dev_err(&pdev->dev, "%pOFn sync own reference\n", np);
1574 of_node_put(args.np);
1575 return -EINVAL;
1576 }
1577
1578 sai->np_sync_provider = of_get_parent(args.np);
1579 if (!sai->np_sync_provider) {
1580 dev_err(&pdev->dev, "%pOFn parent node not found\n",
1581 np);
1582 of_node_put(args.np);
1583 return -ENODEV;
1584 }
1585
1586 sai->sync = SAI_SYNC_INTERNAL;
1587 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
1588 if (!STM_SAI_HAS_EXT_SYNC(sai)) {
1589 dev_err(&pdev->dev,
1590 "External synchro not supported\n");
1591 of_node_put(args.np);
1592 ret = -EINVAL;
1593 goto err_put_sync_provider;
1594 }
1595 sai->sync = SAI_SYNC_EXTERNAL;
1596
1597 sai->synci = args.args[0];
1598 if (sai->synci < 1 ||
1599 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
1600 dev_err(&pdev->dev, "Wrong SAI index\n");
1601 of_node_put(args.np);
1602 ret = -EINVAL;
1603 goto err_put_sync_provider;
1604 }
1605
1606 if (of_property_match_string(args.np, "compatible",
1607 "st,stm32-sai-sub-a") >= 0)
1608 sai->synco = STM_SAI_SYNC_OUT_A;
1609
1610 if (of_property_match_string(args.np, "compatible",
1611 "st,stm32-sai-sub-b") >= 0)
1612 sai->synco = STM_SAI_SYNC_OUT_B;
1613
1614 if (!sai->synco) {
1615 dev_err(&pdev->dev, "Unknown SAI sub-block\n");
1616 of_node_put(args.np);
1617 ret = -EINVAL;
1618 goto err_put_sync_provider;
1619 }
1620 }
1621
1622 dev_dbg(&pdev->dev, "%s synchronized with %s\n",
1623 pdev->name, args.np->full_name);
1624 }
1625
1626 of_node_put(args.np);
1627 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1628 if (IS_ERR(sai->sai_ck)) {
1629 ret = dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck),
1630 "Missing kernel clock sai_ck\n");
1631 goto err_put_sync_provider;
1632 }
1633
1634 ret = clk_prepare(sai->pdata->pclk);
1635 if (ret < 0)
1636 goto err_put_sync_provider;
1637
1638 if (STM_SAI_IS_F4(sai->pdata))
1639 return 0;
1640
1641 /* Register mclk provider if requested */
1642 if (of_property_present(np, "#clock-cells")) {
1643 ret = stm32_sai_add_mclk_provider(sai);
1644 if (ret < 0)
1645 goto err_unprepare_pclk;
1646 } else {
1647 sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK");
1648 if (IS_ERR(sai->sai_mclk)) {
1649 ret = PTR_ERR(sai->sai_mclk);
1650 goto err_unprepare_pclk;
1651 }
1652 }
1653
1654 return 0;
1655
1656 err_unprepare_pclk:
1657 clk_unprepare(sai->pdata->pclk);
1658 err_put_sync_provider:
1659 of_node_put(sai->np_sync_provider);
1660
1661 return ret;
1662 }
1663
stm32_sai_sub_probe(struct platform_device * pdev)1664 static int stm32_sai_sub_probe(struct platform_device *pdev)
1665 {
1666 struct stm32_sai_sub_data *sai;
1667 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
1668 int ret;
1669
1670 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1671 if (!sai)
1672 return -ENOMEM;
1673
1674 sai->id = (uintptr_t)device_get_match_data(&pdev->dev);
1675
1676 sai->pdev = pdev;
1677 mutex_init(&sai->ctrl_lock);
1678 spin_lock_init(&sai->irq_lock);
1679 platform_set_drvdata(pdev, sai);
1680
1681 sai->pdata = dev_get_drvdata(pdev->dev.parent);
1682 if (!sai->pdata) {
1683 dev_err(&pdev->dev, "Parent device data not available\n");
1684 return -EINVAL;
1685 }
1686
1687 if (sai->pdata->conf.get_sai_ck_parent) {
1688 sai->set_sai_ck_rate = stm32_sai_set_parent_clk;
1689 } else {
1690 sai->set_sai_ck_rate = stm32_sai_set_parent_rate;
1691 sai->put_sai_ck_rate = stm32_sai_put_parent_rate;
1692 }
1693
1694 ret = stm32_sai_sub_parse_of(pdev, sai);
1695 if (ret)
1696 return ret;
1697
1698 if (STM_SAI_IS_PLAYBACK(sai))
1699 sai->cpu_dai_drv = stm32_sai_playback_dai;
1700 else
1701 sai->cpu_dai_drv = stm32_sai_capture_dai;
1702 sai->cpu_dai_drv.name = dev_name(&pdev->dev);
1703
1704 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
1705 IRQF_SHARED, dev_name(&pdev->dev), sai);
1706 if (ret) {
1707 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
1708 goto err_unprepare_pclk;
1709 }
1710
1711 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1712 conf = &stm32_sai_pcm_config_spdif;
1713
1714 ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
1715 if (ret) {
1716 ret = dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n");
1717 goto err_unprepare_pclk;
1718 }
1719
1720 ret = snd_soc_register_component(&pdev->dev, &stm32_component,
1721 &sai->cpu_dai_drv, 1);
1722 if (ret)
1723 goto err_deregister_pcm_dma;
1724
1725 pm_runtime_enable(&pdev->dev);
1726
1727 return 0;
1728
1729 err_deregister_pcm_dma:
1730 snd_dmaengine_pcm_unregister(&pdev->dev);
1731 err_unprepare_pclk:
1732 clk_unprepare(sai->pdata->pclk);
1733 of_node_put(sai->np_sync_provider);
1734
1735 return ret;
1736 }
1737
stm32_sai_sub_remove(struct platform_device * pdev)1738 static void stm32_sai_sub_remove(struct platform_device *pdev)
1739 {
1740 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev);
1741
1742 clk_unprepare(sai->pdata->pclk);
1743 snd_dmaengine_pcm_unregister(&pdev->dev);
1744 snd_soc_unregister_component(&pdev->dev);
1745 pm_runtime_disable(&pdev->dev);
1746 of_node_put(sai->np_sync_provider);
1747 }
1748
stm32_sai_sub_suspend(struct device * dev)1749 static int stm32_sai_sub_suspend(struct device *dev)
1750 {
1751 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1752 int ret;
1753
1754 ret = clk_enable(sai->pdata->pclk);
1755 if (ret < 0)
1756 return ret;
1757
1758 regcache_cache_only(sai->regmap, true);
1759 regcache_mark_dirty(sai->regmap);
1760
1761 clk_disable(sai->pdata->pclk);
1762
1763 return 0;
1764 }
1765
stm32_sai_sub_resume(struct device * dev)1766 static int stm32_sai_sub_resume(struct device *dev)
1767 {
1768 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1769 int ret;
1770
1771 ret = clk_enable(sai->pdata->pclk);
1772 if (ret < 0)
1773 return ret;
1774
1775 regcache_cache_only(sai->regmap, false);
1776 ret = regcache_sync(sai->regmap);
1777
1778 clk_disable(sai->pdata->pclk);
1779
1780 return ret;
1781 }
1782
1783 static const struct dev_pm_ops stm32_sai_sub_pm_ops = {
1784 SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume)
1785 };
1786
1787 static struct platform_driver stm32_sai_sub_driver = {
1788 .driver = {
1789 .name = "st,stm32-sai-sub",
1790 .of_match_table = stm32_sai_sub_ids,
1791 .pm = pm_ptr(&stm32_sai_sub_pm_ops),
1792 },
1793 .probe = stm32_sai_sub_probe,
1794 .remove = stm32_sai_sub_remove,
1795 };
1796
1797 module_platform_driver(stm32_sai_sub_driver);
1798
1799 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1800 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
1801 MODULE_ALIAS("platform:st,stm32-sai-sub");
1802 MODULE_LICENSE("GPL v2");
1803